Filter calculations

ACTIVE AND PASSIVE FILTER CALCULATIONS

-Thomas Shaw

Overview

Purpose: Subtract the two sensed signals (Vvs and Vis), apply gain, and low-pass filter the result before the ADC. Derive the frequency response and choose component values for the active filter and the passive RC output filter.

• Input: 500 Hz source signals, Vis (inverting) and Vvs (non-inverting)
• Output: filtered difference signal centred on the 1.65 V reference
• Supply: 5 V and GND (U4B, U5B)
• Target cutoff: 1.5 decades above 500 Hz → 15.81 kHz

Circuit

Item	Description
U5B	Op-amp, 5 V supply
Vis	Signal input, through R20 to the inverting input
Vvs	Signal input, through R22 to the non-inverting input
R19 || C14	Feedback from output to inverting input
R23, C16	Divider and filter at the non-inverting input
Vref	1.65 V reference at the bottom of R23
D7, D9	Input clamp diodes
R21, C30	Passive RC output filter to ADC

Assumptions

• Ideal op-amp: infinite gain, no input current, so V- = V+
• D7 and D9 are open circuits for small-signal AC, so they are ignored
• Vref is DC only. By superposition it only sets the output offset, so set Vref = 0 for the Bode plot
• Notation: w = 2pif, and j is the imaginary unit

Active Filter (Difference Amplifier)

General transfer function

Step 1: Non-inverting node

KCL at V+ (no current into the op-amp):

(Vvs - V+)/R22 + (Vref - V+)/R23 = V+ * jwC16

Multiply through by R22*R23 and solve:

        Vvs*R23 + Vref*R22
V+ = --------------------------------
      R22*R23*jwC16 + R22 + R23

Step 2: Op-amp stage

Feedback impedance (R19 in parallel with C14):

        R19
Zf = --------------
      1 + jw*R19*C14

Output:

Vout = -(Zf/R20) * Vis + (1 + Zf/R20) * V+

In components:

               R19                          R19 + R20*(1 + jw*R19*C14)
Vout = - ------------------------ * Vis + ----------------------------- * V+
          R20 + jw*R20*R19*C14               R20 + jw*R20*R19*C14

Step 3: Combine

Substituting V+ from Step 1:

               R19                          R19 + R20*(1 + jw*R19*C14)     Vvs*R23 + Vref*R22
Vout = - ------------------------ * Vis + ----------------------------- * -------------------------------
          R20 + jw*R20*R19*C14               R20 + jw*R20*R19*C14           R22*R23*jwC16 + R22 + R23

Issue: This has two poles and one zero. The two inputs see different frequency responses, so the circuit is not a true difference amplifier and common-mode rejection is poor.

Matching the two sides

The circuit is a true difference amplifier when the V+ network matches the feedback network:

R23/R22 = R19/R20     and     R22*C16 = R20*C14

Simplest way to meet both:

R23 = R19,   R22 = R20,   C16 = C14

More general family (scales the Vvs network):

R22 = k*R20,   R23 = k*R19,   C16 = C14/k

Simplification

With the matched values, the denominator of V+ becomes:

R22*R23*jwC16 + R22 + R23  ->  R19 + R20 + jw*R19*R20*C14

This is identical to the numerator of the non-inverting gain, so they cancel:

R19 + R20*(1 + jw*R19*C14) = R19 + R20 + jw*R19*R20*C14

Result:

        (R19/R20) * (Vvs - Vis)          Vref
Vout = ------------------------- + ----------------
          1 + jw*R19*C14            1 + jw*R19*C14

• Difference gain: R19/R20
• One low-pass pole at w = 1/(R19*C14)
• Vref passes through with unity DC gain, so it sets the output offset

Bode plot

With Vref = 0:

                 Vout           R19/R20
H(jw) = ------------- = ----------------
          Vvs - Vis       1 + jw*R19*C14

Magnitude

|H| = (R19/R20) / sqrt(1 + (w*R19*C14)^2)

|H|dB = 20*log10(R19/R20) - 10*log10(1 + (w*R19*C14)^2)

Phase

angle(H) = -atan(w*R19*C14)

For the Vis input alone, add 180 degrees (inverting input).

Corner frequency

fc = 1 / (2*pi*R19*C14)

Region	Magnitude	Phase
f << fc	flat at 20*log10(R19/R20) dB	about 0 deg
f = fc	3 dB below passband	-45 deg
f >> fc	falls at -20 dB/decade	tends to -90 deg

Choosing component values

Target cutoff frequency

Cutoff placed 1.5 decades above the 500 Hz source frequency:

fc = 500 * 10^1.5 = 15.81 kHz

• Far enough above 500 Hz that the 500 Hz signal is barely attenuated or phase shifted
• Still low enough to roll off high-frequency noise before the ADC

Resistor values (from gain selection)

Ref	Value	Notes
R19	100 kΩ	Feedback
R20	82 kΩ	Vis input
R22	68 kΩ	Vvs input
R23	100 kΩ	To Vref
R4 / R8	270 kΩ / 15 kΩ	Voltage divider driving Vvs

The divider has a Thevenin resistance that adds in series with R22:

R_th     = R4 || R8 = 14.21 kΩ
R22_eff  = R22 + R_th = 68k + 14.21k = 82.21 kΩ  ≈ R20

So the matching conditions must use R22_eff, not R22:

R23/R22_eff = 100/82.21 = 1.216   ≈   R19/R20 = 1.2195

C14 (feedback capacitor)

C14 = 1 / (2*pi*R19*fc)
    = 1 / (2*pi * 100k * 15.81k)
    = 100.7 pF   ->  100 pF

Resulting cutoff:

fc = 1 / (2*pi * 100k * 100p) = 15.92 kHz   (1.50 decades above 500 Hz)

C16 (non-inverting capacitor)

From the matching condition R22_effC16 = R20C14:

C16 = R20*C14 / R22_eff
    = 82k * 100p / 82.21k
    = 99.7 pF   ->  100 pF

So C16 = C14 = 100 pF. This works because R22_eff ≈ R20 and R23 = R19.

Effect at 500 Hz

|H|/H0  = 1 / sqrt(1 + (500/15.92k)^2) = 0.9995   (-0.004 dB, 0.05% gain error)
angle   = -atan(500/15.92k)            = -1.80 deg

Across the 490–510 Hz source tolerance:

f	Gain error	Phase
490 Hz	0.047%	-1.76°
500 Hz	0.049%	-1.80°
510 Hz	0.051%	-1.84°

The gain error is negligible compared with the ±5% accuracy spec.

Current channel (U4B)

The current amplifier uses the same topology: R11 || C9 feedback, with R12 and C10 at V+. It should use the same fc, so both channels have the same phase lag at 500 Hz. Otherwise the phase difference shows up directly as a power factor error.

C9 = 1 / (2*pi * R11 * fc)
   = 1 / (2*pi * 33k * 15.81k)
   = 305 pF   ->  300 pF

fc = 1 / (2*pi * 33k * 300p) = 16.08 kHz

R12 = R11 and R10 = R9 (no divider in this path), so C10 = C9 = 300 pF.

Channel	R_f	C_f	fc	Phase at 500 Hz
Voltage (U5B)	100 kΩ	100 pF	15.92 kHz	-1.80°
Current (U4B)	33 kΩ	300 pF	16.08 kHz	-1.78°

• Phase mismatch between the channels is about 0.02°, so the power/PF error is negligible
• If 300 pF is unavailable, 330 pF gives fc = 14.6 kHz (-1.96°), a 0.16° mismatch, which is still negligible

Capacitor type

• Use C0G/NP0 ceramics: stable with temperature and voltage, typically ±5%
• C14/C16 and C9/C10 mismatch only affects common-mode rejection near and above fc, not at 500 Hz

Passive RC Output Filter

Values

Ref	Value	Channel
R13	1 kΩ	Current (Vim)
C11	10 nF	Current (Vim)
R21	1 kΩ	Voltage (Vvm)
C30	10 nF	Voltage (Vvm)

fc = 1 / (2*pi*R*C)
   = 1 / (2*pi * 1k * 10n)
   = 15.92 kHz

Why fc = 15.92 kHz

• It matches the active filter corner (15.92 kHz voltage, 16.08 kHz current), keeping the design at 1.5 decades above 500 Hz
• Both channels get identical RC filters, so they get identical extra phase lag, and the phase difference between V and I is unchanged

Combined response (active pole + passive pole)

Two real poles at about the same frequency give a 2nd-order low-pass:

H(jw) = H0 / (1 + jw/wc)^2

|H|/H0  = 1 / (1 + (f/fc)^2)
angle   = -2*atan(f/fc)
f_-3dB  = fc * sqrt(sqrt(2) - 1) = 0.644 * 15.92k = 10.25 kHz

f	Active only	Active + RC
500 Hz	-0.004 dB, -1.80°	-0.009 dB, -3.60°
5 kHz (ADC Nyquist at 10 kHz)	-0.41 dB	-0.82 dB
10 kHz	-1.44 dB	-2.88 dB
159 kHz	-20 dB	-40 dB

• At 500 Hz the gain error is still only 0.1%, far below the ±5% spec
• The roll-off above fc doubles to -40 dB/decade, which improves noise and anti-aliasing rejection
• The cutoff prioritises minimal gain and phase error at 500 Hz over strong anti-aliasing near Nyquist

Phase matching between channels

Channel	Active pole	RC pole	Total at 500 Hz
Voltage	-1.80°	-1.80°	-3.60°
Current	-1.78°	-1.80°	-3.58°

• Mismatch is about 0.02°, so the effect on the calculated power is negligible
• With ±5% capacitor tolerance, the worst-case extra mismatch is about 0.09°. That is about a 0.12% power error at PF = 0.8

Why 1 kΩ

• ADC source impedance: The ATmega328PB datasheet recommends an analogue source impedance of 10 kΩ or less. 1 kΩ is well within this, so the sample-and-hold capacitor charges fully
• Op-amp stability: The resistor isolates the TLC082 output from the 10 nF capacitor. Driving a large capacitive load directly can make an op-amp ring or oscillate
• Fault current limiting: If the op-amp output goes above AREF or to the 5 V rail, 1 kΩ limits current into the ADC pin's protection diodes to a few mA
• Light load on the op-amp: At 500 Hz, X_C = 1/(2pi500*10n) = 31.8 kΩ, so the op-amp sources only about 44 µA peak

Why 10 nF

• Sets fc with a standard value: 1 kΩ and 10 nF are both common values and give exactly 15.92 kHz
• Charge reservoir for the ADC: The ADC sample-and-hold capacitor is about 14 pF. When the multiplexer switches between channels, it shares charge with C11/C30:

dV = dV_channels * C_SH / (C + C_SH)
   = 2.8 V * 14p / 10.014n
   = 3.9 mV (worst case, about 1 LSB)

• The 10 nF capacitor is about 700 times larger than the sample-and-hold capacitor, so the kickback is at most about 1 LSB and recovers through R with τ = R*C = 10 µs
• Use C0G/NP0 for stable capacitance and close matching between channels

Summary

Component	Value	Purpose
C14, C16	100 pF	Voltage channel active pole (15.92 kHz)
C9, C10	300 pF	Current channel active pole (16.08 kHz)
R13, R21	1 kΩ	Passive RC output filter
C11, C30	10 nF	Passive RC output filter (15.92 kHz)

Parameter	Value
Combined -3 dB	10.25 kHz
Roll-off	-40 dB/decade
Gain error at 500 Hz	0.1%
Phase at 500 Hz	-3.6° (same on both channels)
Channel phase mismatch	~0.02°