Support Circuitry Component selection

MCU AND SUPPORT CIRCUITRY

-Thomas Shaw

Overview

Purpose: Document the supporting components around the ATmega328PB, op-amps, level shifter, headers and signal inputs: decoupling, clock, reset, status LED, pull-ups and input protection.

Block	Parts	Value
MCU decoupling	C23 (V_CC), C24 (AV_CC), C25 (AREF)	100 nF X7R
Op-amp decoupling	C26 (U8), C29 (U5), C38 (U4)	100 nF X7R
Level shifter decoupling	C7 (5 V), C8 (3.3 V)	100 nF X7R
Header decoupling	C27, C28, C37, ESP32 header	100 nF X7R
ESP32 bulk	Spare footprint	Electrolytic, optional
Crystal	Y1 (ABLS-16.000MHZ-B4-T)	16 MHz
Crystal load caps	C21, C22	22 pF C0G
Reset	R28 / C31	10 kΩ / 100 nF
I²C pull-ups	R14, R15	Not fitted
Power LED	R24 / D4	470 Ω / LTST-C191KGKT (green, 0603)
Input clamps	D7, D9, D10, D11	3.3 V Zener

Decoupling

Why 100 nF everywhere

• Each IC draws short current spikes when it switches. The supply traces have inductance, so these spikes cause local voltage dips without a nearby capacitor
• A 100 nF ceramic placed at each supply pin supplies those spikes locally
• X7R is used because exact capacitance doesn't matter for decoupling, only low impedance at high frequency
• 100 nF is the standard value: its self-resonant frequency (typically tens of MHz in small packages) covers digital switching noise and the 150 kHz buck ripple
• Using one value everywhere simplifies the bill of materials and assembly

MCU (C23, C24, C25)

Cap	Pin	Purpose
C23	V_CC	Digital supply decoupling
C24	AV_CC	Analogue supply decoupling. Keeps digital switching noise off the ADC supply
C25	AREF	Filters the 3.3 V reference at the pin. Any noise here appears directly in every ADC reading

Op-amps (C26, C29, C38)

• One per dual TLC082 package (U4, U5, U8), on the 5 V supply pin
• Prevents supply noise coupling into the signal path (the op-amps have finite supply rejection) and keeps the outputs stable

Level shifter (C7, C8)

• The TXS0108E has two supplies: V_CCA (3.3 V side, ESP32) and V_CCB (5 V side, MCU)
• One 100 nF capacitor on each supply, as both sides switch

Headers (C27, C28, C37, ESP32)

• Decouple the supply at each off-board connection (I²C screen, 7-segment display, ESP32)
• Off-board modules draw switching current through the header and cable inductance, so local capacitance stops those spikes from disturbing the main rails

ESP32 bulk capacitor (optional)

• A spare footprint is provided for an electrolytic capacitor at the ESP32 header
• The ESP32 draws bursts of ~300 mA during BLE/WiFi transmission
• A bulk capacitor would supply these bursts locally, reducing dips on the 5 V rail
• Only needed if brown-outs or resets are seen during transmission. The LM1117-5.0 output cap (C20, 47 µF) already supports load steps

Clock

Crystal (Y1: 16 MHz)

• The ATmega328PB runs from an external 16 MHz crystal
• The course specification requires a 2 MHz system clock:

f_sys = 16 MHz / 8 = 2 MHz      (CKDIV8 fuse / clock prescaler)

• A crystal gives far better frequency accuracy than the internal RC oscillator (~±10% before calibration), which matters for:
  • UART at 9600 baud (needs < ~2% error)
  • accurate timer-based sampling and the 1 s display scroll

Load capacitors (C21, C22 = 22 pF)

The crystal is specified for a particular load capacitance (C_L). The two caps appear in series, plus stray PCB/pin capacitance:

C_L = (C21 × C22) / (C21 + C22) + C_stray
    = (22 × 22) / 44 + ~5 pF
    ≈ 11 + 5 = 16 pF

• Close to typical crystal load specs (~18 pF), so the oscillator runs at its rated frequency
• C0G is used because capacitance must be stable with temperature, or the frequency drifts
• 22 pF is the standard value recommended for ATmega crystal oscillators

Reset (R28, C31)

R28 = 10 kΩ pull-up to 5 V
C31 = 100 nF to GND
τ = R28 × C31 = 10k × 100n = 1 ms

• R28 holds RESET high in normal operation. The pin has a weak internal pull-up, but an external 10 kΩ gives better noise immunity, as recommended for AVR designs
• C31 holds RESET low for ~1 ms at power-up while the supply settles, and filters noise spikes that could cause false resets
• The ISP header drives RESET directly. Its strong driver overrides the RC, so programming still works
• Note: if debugWIRE debugging is ever used, C31 must be removed, as it interferes with debugWIRE communication on the RESET pin

I²C Pull-ups (R14, R15): not fitted

• I²C (TWI) needs pull-up resistors on SDA and SCL
• The I²C screen module already has pull-ups on its own PCB
• Fitting R14/R15 as well would place them in parallel, lowering the total pull-up resistance and increasing the current the bus drivers must sink
• The footprints are kept in case a screen without on-board pull-ups is used

Power LED (R24, D4)

Part: LTST-C191KGKT (Lite-On), 0603, yellow-green (~570 nm)

Parameter	Value
Forward voltage V_F	~2.0 V typ, 2.4 V max
Max DC forward current	30 mA
Luminous intensity	~35 mcd (at 20 mA)
Power dissipation (max)	75 mW

Connected to the 7 V rail, so it lights only when the buck converter is running. That makes it a quick visual check of the first regulation stage.

I_LED = (V_7V − V_F) / R24
      = (7.0 − 2.0) / 470 = 10.6 mA   (V_F typ)
      = (7.0 − 2.4) / 470 = 9.8 mA    (V_F max)

P_R24 = I_LED² × R24 = 0.0106² × 470 = 53 mW
P_LED = I_LED × V_F  = 0.0106 × 2.0  = 21 mW

Parameter	Value	Limit	OK
R24	470 Ω (E12)	—	—
I_LED	9.8–10.6 mA	30 mA	✅
P_LED	21 mW	75 mW	✅
P_R24	53 mW	Resistor package rating	✅ (0805 or larger)

• ~10 mA gives clearly visible brightness, about half the LED's 20 mA rated test current
• Well within the LED's current and power limits
• Adds ~10 mA to the 7 V rail load, small compared with the buck converter's capacity

Input Clamps (D7, D9, D10, D11)

Parts: 3.3 V Zener diodes, connected back-to-back from each sensing input (Vis, Vvs) to GND

Clamp level ≈ ±(V_Z + V_F) ≈ ±(3.3 + 0.7) ≈ ±4.0 V

Input	Normal peak	Clamp	Conducts normally?
Vis	±0.42 V	±4.0 V	No
Vvs	±~1.5 V	±4.0 V	No

• In normal operation neither input gets close to the clamp level, so the Zeners do not affect measurements
• Under a fault (for example the shunt or divider becoming disconnected, or a wiring error exposing an input to the 21.8 V peak source), the Zeners clamp the input and protect the op-amp inputs
• Back-to-back placement clamps both polarities, which is needed because the sensed signals are AC
• Consideration: low-voltage Zeners have a soft knee and leak slightly below V_Z. On the Vvs node (14.2 kΩ source impedance) a few µA of leakage could add a small error. This was not observed as significant in testing

Summary

Component	Value	Reason
All decoupling	100 nF X7R	Local high-frequency supply at each IC and header
ESP32 bulk	Optional electrolytic	Spare footprint for BLE burst current
Y1	16 MHz ÷ 8	2 MHz system clock, accurate UART timing
C21, C22	22 pF C0G	Crystal load ≈ 16 pF
R28 / C31	10 kΩ / 100 nF	Reset pull-up, 1 ms power-on delay
R14, R15	Not fitted	Pull-ups already on screen PCB
R24 / D4	470 Ω / LTST-C191KGKT	~10 mA power indicator on 7 V rail
D7, D9, D10, D11	3.3 V Zener	±4 V input fault clamps

References

• LTST-C191KGKT (Flux/LCSC)
• LTST-C191KGKT (RS Components)
• ATmega328PB datasheet (Microchip)
• TXS0108E datasheet (Texas Instruments)