RV-SIIOS (RISC-V Single-Issue In-Order Scalar)

This cpu is 2-stage scalar processor.

SPECIFICATIONS

Architecture

• RV32-IMC
• Fast and slow option for multiplication unit
• Slow division unit

Memory

• Neumann bus architecture
• Unified Tightly Integrated Memory

Peripheral

• UART
• Baudrate 115200
• Start Bit
• Stop Bit
• 8 Data Bits
• No Parity Bit

TOOLS

The installation scripts of necessary tools are located in directory tools. These scripts need root permission in order to install packages and tools for simulation and testcase generation.

USAGE

1. Clone the repository:

git clone --recurse-submodules https://github.com/taneroksuz/rv-siios.git

2. Install necessary tools for compilation and simulation:

make tool

3. Compile some benchmarks:

make compile

4. Compiled executable files are located in riscv and dumped files are located in dump. Select an executable and run simulation:

make verilator PROGRAM=coremark

5. Run simulation with debug feature:

make verilator DUMP=1

6. Run simulation with short period of time (e.g 1us, default 10ms):

make verilator MAXTIME=1000

7. The simulation results together with debug informations are located in sim/verilator/output.

BENCHMARKS

Coremark Benchmark

Cycles	Iteration/s/MHz	Iteration
339800	2.94	10