Verilog Codes for various digital circuits for labs at IIT Ropar, basic gates, adders & subtractors (half & full), ripple adders, multipliers and code converters.
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Updated
May 11, 2017 - Verilog
Verilog Codes for various digital circuits for labs at IIT Ropar, basic gates, adders & subtractors (half & full), ripple adders, multipliers and code converters.
Complex Adder with Seven Segment Display
Source code for various Verilog-based projects and assignments
Implementing Different Adder Structures in Verilog
This repository contains source code for past labs and projects involving FPGA and Verilog based designs
A carry select adder is an arithmetic combinational logic circuit which adds two N- bit binary numbers and outputs their N-bit binary sum and a 1-bit carry.
All the fundamental generic verilog modules in one repository. These are fundamentals by my standard, so feel free to suggest more.
FPGA design for implementing encoder, adder and counter circuits. (using logic tiles and switch boxes)
Embedded Systems Lab Work
In computer engineering, computer architecture is a set of rules and methods that describe the functionality, organization, and implementation of computer systems.
Performed a comparative study of Parallel Prefix Adders using Verilog HDL on Zynq-7000 APSoC (PL) from XIlinx. Circuits are simulated, synthesized and implemented using Vivado Design Suite.
Computer Architecture -VLSI -Verilog Codes-Xilinx-Irsim
Verilog for ASIC Design
Implementation of a simple SIMD processor in Verilog, core of which is a 16-bit SIMD ALU. 2's compliment calculations are implemented in this ALU. The ALU operation will take two clocks. The first clock cycle will be used to load values into the registers. The second will be for performing the operations. 6-bit opcodes are used to select the fun…
Digital System Design Lab Codes using Verilog
Combinational adder and multiplier modules for IEEE 754 single-precision and double-precision floating point format.
CSE-2112 Digital Syatem Design LAb
Open Source Verilog Modules
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