UVM Test bench for a 8-bit ALU

This is a modified version of the 32-bit MIPS microprocessor. Please refer to "manual.pdf" for more information.

Simple arithmetic logic unit

32 bits CLA(Carry Lookahead Adder) and ALU RTL and verification. 32位块间超前的超前进位加法器及ALU设计与验证

A simple arithmetic logic unit (ALU) with System verilog

SystemVerlilog-Projects

An ALU implementation in System Verilog. Course project: Code upon request.

Syntacore scr1 iALU verification example

10-bit MDR (Multiplication, division and square root calculator) implemented for the FPGA DE2-115 and for a ModelSim simulation. Coded in System Verilog ⚙️

This project is a 32-bit Arithmetic Logic Unit (ALU) designed in SystemVerilog as part of a MIPS microprocessor simulation. The ALU supports various arithmetic and logical operations and includes a custom-built 32-bit full adder, one 2-to-1 MUX, one 4-to-1 MUX, one AND gate , one OR gate and the Zero Extend Logic