A mixed-criticality platform built around Cheshire, with a number of safety/security and predictability features. Ready-to-use FPGA flow on multiple boards is available.
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Updated
Aug 29, 2024 - Tcl
A mixed-criticality platform built around Cheshire, with a number of safety/security and predictability features. Ready-to-use FPGA flow on multiple boards is available.
Implementation of Timing Exceptions in RTL design for STA
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High-Level Synthesis project for latency optimisation under area constraints
Tiny Tapeout 04 Logic IC. Erics submission of his first real microchip doing basic safety chain control
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