axi
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VHDL design for rotary encoder. Can be used accessed via digital signals or AXI interface.
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Mar 24, 2017 - VHDL
IP core for a simple SPI master with variable clock frequncy within AXI peripheral. Developed and tested on Zybo evaluation board (Zynq-7000 product family)
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Jul 12, 2017 - VHDL
ASIC for executing vectorized gradient descent on linear regression problems.
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Aug 13, 2018 - VHDL
Example workflow project for VHDL development.
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Feb 18, 2023 - VHDL
FPU that does all the 4 fundamental arithmetic operations made as an AXI-Lite Slave IP in AMD Vivado. IEEE 754 was used. It can be successfully implemented on an Arty S7-50 FPGA board.
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Apr 13, 2024 - VHDL
3 stage pipeline implementation of a digital circuit that calculates DIT FFT in 8 points. It is made as an AXI-Lite Slave IP in AMD Vivado. It is successfully implemented in a block design that contains a Microblaze processor as the Master, an AXI Interconnect as the Bridge and the AXI-Lite FFT IP as Slave.
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Apr 13, 2024 - VHDL
FPGA interface and driver for an OV7670 camera sensor.
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Aug 28, 2023 - VHDL
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