basys3

Here are 3 public repositories matching this topic...

Prajjv / RISC-V-Microprocessor-verilog-code-implementation-Artix-7-tested-with-Fibonacci-series-on-7seg

Here we are implementing Risc-V single cycle microprocessor on Basys3 (Artix-7) .We are testing with Fibonaccie Series and showing on 7 segment display..

verilog microprocessor vivado fibonacci-numbers 7-segment risc-v fibonacci-sequence basys3 vivado-hls artix-7 basys3-fpga single-cycle-processor basys3-fpga-board

Updated Dec 7, 2022
Tcl

krish1925 / CS-M152A

Star

Labwork on Logic Design implementation in Verilog on a Basys3 FPGA Module

modular verilog uart basys3 modular-design half-adder full-adder fpga-programming 7-segment-display

Updated Apr 13, 2024
Tcl

suoglu / AXI-lite-slave

Star

Slaves for AXI-lite interface

gpio fpga basys3 arty nexys-video axi-lite

Updated Aug 3, 2023
Tcl

Improve this page

Add a description, image, and links to the basys3 topic page so that developers can more easily learn about it.

Curate this topic

Add this topic to your repo

To associate your repository with the basys3 topic, visit your repo's landing page and select "manage topics."

Learn more

Provide feedback

Saved searches

Use saved searches to filter your results more quickly