Harvard (separate memories for data and instructions), RISC-like, five-stages pipeline processor
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Updated
Jan 29, 2023 - Verilog
Harvard (separate memories for data and instructions), RISC-like, five-stages pipeline processor
Branch Prediction Experiments
Contains source code to carry out tests & analyse the results of various branch predictors against each other. Additionally, demonstrates the benefits of cache-oblivious algorithms. Done as part of VL-803 Processor Architecture course at IIIT-B (Spring 2020).
Syracuse University CIS657 research paper: what is the optimal choice of branch prediction method?
Trabalhos apresentados como requisito parcial à conclusão da disciplina "CI086 - Tópicos em Arquitetura de Computadores" da UFPR, feitos no ambiente do simulador de instruções Orcs. A referência mais atual para esse simulador pode ser encontrada em: https://github.com/mazalves/OrCS
Some tests on SSE and branch prediction
C++ Macro definitions for easy branch hinting.
Simulation of CPU cache and branch predictor algorithms
System of branch prediction based on simple perceptron. Fast path-based and idealized piecewised predictor.
Investigating the use of hint bits in JUMP statements for pipelined CPU branch predictors
Educational project aimed at evaluating the effectiveness of different correlating branch predictors on benchmarks
Implementation of 4 different branch predictors in C
A pipelined implementation of a MIPS processor that was optimized to use data forwarding, caching and branch prediction.
Implemented an algorithm to simulate the use of dynamic branch prediction schemes
Simulation of a bimodal two-level single branch/jump predictor, implemented in Python, for High Performance Processors (2022-23).
Branch Prediction Simulator(Smith N-bit, Bimodal, GShare, Hybrid) implemented in Python3
VHDL code of three branch predictors
Pathfinder: High-Resolution Control-Flow Attacks Exploiting the Conditional Branch Predictor
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