Collection of utility modules written in Verilog
-
Updated
Aug 3, 2023 - Verilog
Collection of utility modules written in Verilog
A real time clock module is designed and simulated in ModelSim. The language used is Verilog HDL.
Add a description, image, and links to the counters topic page so that developers can more easily learn about it.
To associate your repository with the counters topic, visit your repo's landing page and select "manage topics."