Calculator on FPGA

VHDL code to generate 2 or 3 phases low precision signals with high frequency master clock

Altera EPM240 playground

RAM and ROM board expansion for the MAXV DeltaBrd

Frequency counter implemented with CPLD EPM3064 only and HDSP-2113 display

LED Wall Screen Buffer and Panel Management Controller in VHDL

6位简易处理器的硬件设计，使用VHDL语言开发，在DE2-115开发板上运行通过。

FPGA and CPLD programming, tutorials and information I figure out.

The project that make by VHDL

MAX7219 7-segment 8-digit LED driver for FPGA/CPLD written in VHDL with cascade connected modules support

My digital clock with Altera's CPLD EPM3064 and 8 digits 7-segment display hh:mm:ss.ds

A small game written in VHDL implemented on a CPLD.

A Sharp MZ80A Video upgrade. v1.0 allows switchable 40/80 column display with colour monitor output, v2.0 provides full pixel graphics compatible with the MZ80B.

My bachelor's degree final year project: A CPLD implementation of a 16-bit microprocessor I learnt from Computer System Architecture by M. Morris Mano

Karabas-128. ZX Spectrum 128k clone, based on CPLD Altera EPM7128STC100