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crossbar

Here are 3 public repositories matching this topic...

dpretet / axi-crossbar

An AXI4 crossbar implementation in SystemVerilog

arm asic fpga processor riscv verilog soc fpga-soc interconnect amba crossbar riscv32 axi4 axi4-lite riscv64 monodraw axi4-protocol asic-design axi4-full

Updated Nov 11, 2024
SystemVerilog

dpretet / friscv

RISCV CPU implementation in SystemVerilog

asic fpga assembler riscv verilog systemverilog fpga-soc risc-v rv32i crossbar axi4 axi4-protocol asic-design riscv-cpu

Updated Oct 8, 2024
SystemVerilog

WbXbc

hotwolf / WbXbc

HDL components to build a customized Wishbone crossbar switch

verilog hdl wishbone crossbar

Updated May 30, 2019
SystemVerilog

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