Implementing a 4-bit Kogge Stone Adder (a type of carry-tree adder) in VHDL using XIlinx Vivado
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Updated
Jul 24, 2023 - VHDL
Implementing a 4-bit Kogge Stone Adder (a type of carry-tree adder) in VHDL using XIlinx Vivado
Final project: Tic-tac-toe on VGA monitor. ENGS31/CS56 Digital Electronics @ Dartmouth.
Códigos dos exercícios do livro Sistemas Digitais: Princípios e Aplicações - 10.ed.
VHDL, FPGA, Fron nand to tretris,
Pong game on FPGA Max 10 DE10-Lite, written in VHDL.
Laboratories of 'Microelectronic Systems' course at PoliTo
Modelling and simulation of a polynomial evaluator in VHDL using stepwise refinement.
Modeling, Design and ASIC implementation of a tenth order FIR filter. This project has been developed in two versions: a basic one, and an improved one using 3-level unfolding and five stages pipeline.
Design and development of a complete RISC CPU with: five stage pipeline, forwarding, automatic hazard detection, BTB using LRU policy replacement, four-cycle hardware multiplier.
Teamwork project of a reflexes analyzer made during the course "Sistemi Digitali Integrati" (Integrated Digital Systems) @ Politecnico di Torino
Some basic VHDL projects.
An 8-bit processor in VHDL based on a simple instruction set
VHDL Lab Exercises from simple Combinational/Sequential circuits to a simple CPU design
basic simulations of digital electronics using vhdl
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