dram
Here are 44 public repositories matching this topic...
DRAM Request Manager for Multicore Processors
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May 27, 2021 - C++
Design of a simulator of a multi-core processor and DRAM for a subset of MIPS instruction set architecture in C++. Course Project of COL216: Computer Architecture taught in Second Sem, 2020-21 at IIT Delhi
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Dec 9, 2021 - C++
Test DRAM for bit flips caused by the rowhammer problem
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Sep 2, 2015 - C++
MIPS simulator, which implements reordering of DRAM requests during runtime to reduce the clock cycles during execution
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May 24, 2021 - C++
A multi-core MIPS simulator with Memory Request Manager for reordering DRAM requests to maximise throughput
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May 23, 2021 - C++
A Multi-core MIPS ISA, with MRM and DRAM, Simulator. Prints what is happening in every clock cycle and the final content of registers and DRAM.
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May 25, 2021 - C++
Behavioral architecture of a read/write cycle controller for a DRAM chip.
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May 26, 2023 - VHDL
MIPS ISA simulator which implements non-blocking DRAM access
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May 24, 2021 - C++
A curated list of awesome Rowhammer papers, tools, and info resources. 👉 Content coming soon, stay tuned!
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Jun 17, 2022
A library that allows the Arduino UNO to read/write to old DIP-style DRAM chips
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Sep 15, 2018 - C++
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