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gtkwave
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Simulation platform that enables VHDL-style C++ coding. VCD generation for easy debug. VHDL code generation using C preprocessor. Simple risc-V rv32i SoC example, + Risc-V test suite and gcc bare-metal example. Linux (or WSL) / clang or gcc / risc-v toolchain / quartus required
c-plus-plus
arduino
simulator
fpga
vhdl
rtl
gtkwave
risc-v
vcd
de10-lite
vidor
rtl-files
rtl-generation
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May 29, 2021 - C
VSDSquadron Research Internship 2024 program where we learn about RISC-V processor and VLSI Design using various open source tools.
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Updated
May 12, 2024 - C
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