building a computer
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Updated
Apr 25, 2019 - Assembly
building a computer
An implementation of mips architecture on FPGA using verilog
Yahtzee game designed in VHDL for Digital System Design Course in EPFL BA2 (IC Section) Grade: 88.89%
Verilog sources for Hardware Lab Assignments
Svart is an embedded (in Dart) domain-specific language for describing binary circuits, generating a strict subset of SystemVerilog and easily interacting with external tools.
Logic Analyzer IP Core
Building a computer from scratch to Tetris
Communication of a CPLD with the analog-to-digital converter ADC0832 (modeled in VHDL)
Verilog structural model HDL program
Computer Science Master program files, assignments and projects
RISC-V is an open-source instruction set architecture (ISA), enabling the implementation of central processing units (CPUs) or system-on-a-chip (SoC) designs without licensing fees. This makes it highly favored among FPGA enthusiasts for softcore processor implementations.
B.Tech CSE @ NITC
Time domain to logarithmic frequency domain converter, as the polyphase FFT do for the linear.
This is digital design project written in Verilog.
Projeto Final da Disciplina de Circuitos Lógicos II em Verilog usando a IDE do Quartus II
SUTD ISTD 2020 Computation Structures Electronic Hardware 1D Project
Building a modern computer from first principles. (Projects from the nand2Tetris computer systems course)
Course Project for EE224 (Digital Systems) offered in Autumn 2023
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