Verilog implementation of an ordinary differential equation (ODE) solver accelerator chip ― **INCOMPLETE IMPLEMENTATION**
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Updated
Jun 19, 2020 - Verilog
Verilog implementation of an ordinary differential equation (ODE) solver accelerator chip ― **INCOMPLETE IMPLEMENTATION**
Student-project
This repository holds files related to the development of a Single-Cycle Processor developed during the Digital Systems Architecture course.
Verilog code for my paper that proposes a secure-AES algorithm with support for various FPGA boards.
Design for 4 bit ALU with essential logical and arithmetic modules.
FPGA design that can apply basic filters to the image data using block ram.
Simple CPU design using the Xilinx ISE tool
Repository for 2nd laboratory activity of CS's Organização e Arquitetura de Computadores (Computer Organisation and Architecture) course at Universidade de Brasília.
An implementation of mips architecture on FPGA using verilog
implementation of a basic computer having ability to perform logic and arithmetic operations
Sngle-cycle, Multi-cycle and Pipeline MIPS implementations; Spring 2022
Repository for my VLSI I final project. We build a naive ML processor in Verilog and simulated and synthesised it using Cadence Tools.
This repository contain basic verilog codes which include the implementation of DLD (digital logic desgin ) circuits.
RISC-V is an open-source instruction set architecture (ISA), enabling the implementation of central processing units (CPUs) or system-on-a-chip (SoC) designs without licensing fees. This makes it highly favored among FPGA enthusiasts for softcore processor implementations.
Application of the RANSAC algorithm in embedded C and Verilog for Altera Nios II and Cyclone IV E.
Some basic hardware and logic designs and their respective testbenches written in Verilog HDL
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