An exploration of a circuit description language for general circuits using rust. In particular PCB's.

Project file made on Quartus in Verilog. With components: Ripple Carry, Full Adder and Half Adder

Build for a blog: https://smirnovich.github.io/

Functional assays development for HDL and Plasma: Data analyses, visuals, reports

Project for Logic Design 2 course taken during Spring 2022 semester. We implemented the Advanced encryption standard (AES128, AES192, AES256) in this project using Verilog and used a wrapper module on the DE1-SOC kit to test it.

Node-Red implementation of HDL BusPro (SmartBus) protocol http://hdlautomation.com

A final project for FPGA_SOC course

An International Obfuscated *HDL Code Contest (Why Verilog? For the name to be good: IOVCC)

ALUminium is a CPLD/FPGA code for a 8bits arithmetic–logic unit, made for processor like GP8B

8-bit ALU in Verilog.

Two Sobel filters designed in VHDL and HLS with Vivado Tools and implemented in ZYBO SoC

HDL, Linux and other guidelines, applications, articles

Sharif University of Technology - Spring 2019 - Digital System Design Course Project

custom lambda-function like circuits for FPGA is the future

HDL for Node-RED, utilizing pure JavaScript HDL Buspro driver