XLS: Accelerated HW Synthesis
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Updated
Jul 11, 2024 - C++
XLS: Accelerated HW Synthesis
A collection of extensions for Vitis and Intel FPGA OpenCL to improve developer quality of life.
Scalable systolic array-based matrix-matrix multiplication implemented in Vivado HLS for Xilinx FPGAs.
FPGA Accelerator for CNN using Vivado HLS
PandA-bambu public repository
Examples shown as part of the tutorial "Productive parallel programming on FPGA with high-level synthesis".
CHARM: Composing Heterogeneous Accelerators on Versal ACAP Architecture
High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS
A graph linear algebra overlay
Tutorials on HLS Design
HeteroCL-MLIR dialect for accelerator design
FPGA acceleration of arbitrary precision floating point computations.
Near-storage compute aware file system and FPGA operator pipelines.
HLS for Networks-on-Chip
Monte Carlo Methods applied to the Black-Scholes financial market model
Systolic Three Matrix Multiplier for Graph Convolutional Networks using High Level Synthesis
AIM: Accelerating Arbitrary-precision Integer Multiplication on Heterogeneous Reconfigurable Computing Platform Versal ACAP (Full Paper accepted to ICCAD2023)!
Fast Floating Point Operators for High Level Synthesis
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