high-level-synthesis

Here are 4 public repositories matching this topic...

ngiambla / qvmi

Quick Verilog Module Isolator - Isolates a design for testing.

fpga regex cpp11 verilog vivado hdl verilog-hdl xilinx-fpga quartus-prime high-level-synthesis dut vivado-hls isolator isolated-modules intel-quartus

Updated Dec 11, 2018
Verilog

BabarZKhan / Kiwi-compiler-HLS

Star

Kiwi was developed at the University of Cambridge Computer Laboratory and Microsoft Research Limited, headed by **David Greaves (UoCCL)** and **Satnam Singh (MRL)**

fpga compiler hardware parallel high-level-synthesis

Updated Sep 5, 2022
Verilog

socks2309 / neural-network-fpga

Star

This project is part of the B.Tech degree in Electronics and Telecommunication Engineering at KIIT University.

neural-network verilog-hdl c-programming high-level-synthesis fpga-programming

Updated Oct 22, 2024
Verilog

AXE-jp / ros2rapper

Star

Hardware implementation of the protocol for ROS2

asic fpga ros2 high-level-synthesis rtps

Updated Sep 26, 2024
Verilog

Improve this page

Add a description, image, and links to the high-level-synthesis topic page so that developers can more easily learn about it.

Curate this topic

Add this topic to your repo

To associate your repository with the high-level-synthesis topic, visit your repo's landing page and select "manage topics."

Learn more

Provide feedback

Saved searches

Use saved searches to filter your results more quickly

high-level-synthesis

Here are 4 public repositories matching this topic...

ngiambla / qvmi

BabarZKhan / Kiwi-compiler-HLS

socks2309 / neural-network-fpga

AXE-jp / ros2rapper

Improve this page

Add this topic to your repo