🚦 A digital controller to control traffic in Verilog HDL
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Updated
Aug 12, 2019 - Verilog
🚦 A digital controller to control traffic in Verilog HDL
This repository focuses on designing and simulating logical circuits using Verilog HDL (Hardware Description Language) with the Icarus Verilog simulator.
A simple up-down counter project made using icarus verilog as a part of the Digital Design and Computer Organization course (UE19CS207) at PES University.
Beginner-level university work on low-level programming and understanding of digital computing components.
Emulating a seven-segment display for Verilog debugging purposes.
Un-pipelined partial MIPS processor implementation in Verilog
This project simules the basic functions of PIC16F84a.
🔐 Hardware Implementation Of AES Algorithm in Verilog HDL
☎️ UART Communication Implementation in Verilog HDL
16 bit IEEE floating point implementation or the UK PinKY pipelined processsor architecture.
This repo consists of the iverilog implementation of a Parallel Prefix adder - 8bit (I/P - O/P). This was done as a part of a project Under UE19CS206 - Digital Design and Computer Organization Laboratory Course at PES University.
A Repo that contains the source code for Digital Design and Computer Organisation course.
Some basic hardware and logic designs and their respective testbenches written in Verilog HDL
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