Exercício 02 de SystemVerilog
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Updated
Dec 8, 2016 - SystemVerilog
Exercício 02 de SystemVerilog
A universal device that allows improving modern traffic lights and adapting them for people with disabilities.
Execício 1 de SystemVerilog
3 stage pipeline implementation of a digital circuit that calculates DIT FFT in 8 points. It is made as an AXI-Lite Slave IP in AMD Vivado. It is successfully implemented in a block design that contains a Microblaze processor as the Master, an AXI Interconnect as the Bridge and the AXI-Lite FFT IP as Slave.
Python I2C driver for 3rd party ST LPS22 pressure sensor
The Internet of Stranger Things (IoST) is an IoT project using the Blynk service, the Arduino compatible Adafruit Feather WiFi board, and WS2811 individually programmable LEDs. Other optional components are included in this particular build of the project that do not effect its overall functionality. Such items will be described within the sourc…
Project made in Introduction to Microelectronics class
AVR's ATMega328P in chip form with castellated pins
The engineering repport for the CAN-FLASH microelectronics project at the Grenoble Institute of Technology
Implementation of a Ring Oscillator-based Physically Unclonable Function (PUF) in Sky130, with 8 bits of Challenge-Response Pairs (CRP)
An UART Receiver that runs with a clock frequency of 125 MHz. The possible baudrates are 9600 bits per second and 115200 bits per second. It supports the parity bit. The received bytes are stored in a FIFO buffer with variable size.
Emacs Org-mode course-work example.
Laboratories of 'Microelectronic Systems' course at PoliTo
ELEEOBO2O MICROELECTRONICS 编程辅导, Code Help, WeChat: powcoder, CS tutor, powcoder@163.com
Workspace di MCUXpresso IDE, utilizzato per la programmazione della LPC845 Breakout Board durante il corso di Microelettronica (Università di Roma Tre)
FPU that does all the 4 fundamental arithmetic operations made as an AXI-Lite Slave IP in AMD Vivado. IEEE 754 was used. It can be successfully implemented on an Arty S7-50 FPGA board.
Matlab simulations about microelectronic systems
4 stage pipeline implementation of a 16-bit RISC Processor in SystemVerilog that performs arithmetical, logical, data transfer, branch and halt operations.
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