Final project for an advanced course in computer architecture, involving a full processor design and assembly code to run a game of Tic-Tac-Toe
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Updated
Nov 1, 2017 - Verilog
Final project for an advanced course in computer architecture, involving a full processor design and assembly code to run a game of Tic-Tac-Toe
🎓Assignment for CE2003 - Digital System Design
a single cycle cpu based on MIPS32 with verilog
Verilog / MIPS / assembly projects
MIPS Verilog implementation with pipeline , Cache and SRAM
This repository holds files related to the development of a Single-Cycle Processor developed during the Digital Systems Architecture course.
MIPS processor designed in Verilog.
Computer architecture course team project
VeriLog and MIPS ASM code that I used in Computer Organization and Architecture course in Amrita.
A simple implementation of a non-pipelined MIPS processor.
Verilog descriptions of MIPS single-cycle, multi-cycle & booth multiplier.
RISC Processor Verilog (2020-2021)
Contains MIPS and Verilog programs done in Computer Architecture Lab
Implementation of MIPS Processor Modules Using Verilog
Designed the revised single-cycle datapath and revised control units which make a processor that executes the instructions as well as the instructions implemented already in the design.
This is a functioning MIPS CPU designed in Verilog to run an an xilinx fpga.
This is a single cycle processor, which processes each instruction in single clock cycle, working on Instruction Set Architecture (ISA) specified in the documentation.
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