NonTrivial-MIPS is a synthesizable superscalar MIPS processor with branch prediction and FPU support, and it is capable of booting linux.
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Updated
Jul 7, 2020 - SystemVerilog
NonTrivial-MIPS is a synthesizable superscalar MIPS processor with branch prediction and FPU support, and it is capable of booting linux.
Single Cycle 32 bit MIPS
MIPS32 CPU implemented in SystemVerilog, with superscalar and branch prediction support
SUSTech CS202/CS214 Computer Organization Project. Streams Bad Apple.
A synthesizable simplified MIPS written in System Verilog
A complete hardware description of a non-pipeline MIPS processor in SystemVerilog that can execute integer assembly code implemented on the Altera DE2-115 FPGA.
A simplified MIPS machine simulator using SystemVerilog, developed with three different micro-architectures: single-cycle, multi-cycle and pipelined.
MIPS architecure processor on Intel FPGA.
Mips Multi-Cycle, Computer Architecture course, University of Tehran
It's a simple verilog based MIPS microarchitecture hardware design.
MIPS written in System Verilog
Mips Single-Cycle, Computer Architecture course, University of Tehran
This is a modified version of the 32-bit MIPS microprocessor. Please refer to "manual.pdf" for more information.
A Developer version MIPS processor.
A complete hardware description of a pipeline MIPS processor in SystemVerilog that can execute integer assembly code implemented on the Altera DE2-115 FPGA. It also has the ALMa Mips Mounter built-in.
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