Matrix multiplication on multiple Nios II cores

Connect a modern, high-resolution camera to an FPGA and easily develop your applications

POSIX-compatible tiny multi-threading library for Intel Nios II / Xilinx Zynq-7000

Garfield (ALF 2.0)@ OTH Regensburg, seeing @

Frogger-inspired game, set in the Toronto area. Built for Terasic's DE1-SoC platform.

Assorted Verilog that brings up different elements (VGA, Ethernet, Switches, LED, LCD, etc.) of the terasIC DE2-70 Development Board.

Hardware Description Languages

C applications for NIOS soc

Code from FPGA programming with the Altera Nios II

SHA-1 implementation on Nios II soft-core processor with C and SystemVerilog.