risc-v
Unlike most other ISA designs, the RISC-V ISA is provided under open source licenses that do not require fees to use. A number of companies are offering or have announced RISC-V hardware, open source operating systems with RISC-V support are available and the instruction set is supported in several popular software toolchains.
Notable features of the RISC-V ISA include a load–store architecture, bit patterns to simplify the multiplexers in a CPU, IEEE 754 floating-point, a design that is architecturally neutral, and placing most-significant bits at a fixed location to speed sign extension. The instruction set is designed for a wide range of uses. The base instruction set has a fixed length of 32-bit naturally aligned instructions, and the ISA supports variable length extensions where each instruction could be an any number of 16-bit parcels in length. Subsets support small embedded systems, personal computers, supercomputers with vector processors, and warehouse-scale 19 inch rack-mounted parallel computers.
Here are 328 public repositories matching this topic...
NCKU Computer Organization 2023
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Aug 11, 2023 - C
The WIOM: A RV32IM In-Order pipelined cpu with no cache and a naive branch predictor.
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Jun 23, 2023 - C
This is a mirror repository of Project SHAKTI SoCs FPGA Emulation.
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Jul 8, 2020 - C
Herramienta que permite la visualización de los resultados obtenidos de la exploración del diseño de microarquitecturas y procesadores. 🧭📊
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Nov 26, 2021 - C
Пример проекта под микроконтроллер K1986VK025 для VS Code с использованием CMake
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Feb 20, 2023 - C
A simple educational operating system for the RISCV architecture
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Jan 4, 2024 - C
ARINC653 Multi-Partition Operating System Based On RISC-V, capable of running on SiFive HiFive Unmatched.
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Jun 25, 2023 - C