RISC-V
Unlike most other ISA designs, the RISC-V ISA is provided under open source licenses that do not require fees to use. A number of companies are offering or have announced RISC-V hardware, open source operating systems with RISC-V support are available and the instruction set is supported in several popular software toolchains.
Notable features of the RISC-V ISA include a load–store architecture, bit patterns to simplify the multiplexers in a CPU, IEEE 754 floating-point, a design that is architecturally neutral, and placing most-significant bits at a fixed location to speed sign extension. The instruction set is designed for a wide range of uses. The base instruction set has a fixed length of 32-bit naturally aligned instructions, and the ISA supports variable length extensions where each instruction could be an any number of 16-bit parcels in length. Subsets support small embedded systems, personal computers, supercomputers with vector processors, and warehouse-scale 19 inch rack-mounted parallel computers.
Here are 86 public repositories matching this topic...
VSDMemSOC Implementation flow:: RTL2GDSII
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Mar 1, 2024 - Verilog
This project involves the development and enhancement of a RISC Stored-Program Machine (RISC SPM), based on the architecture detailed in "Advanced Digital Design with the Verilog HDL" by Michael D. Ciletti.
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May 4, 2024 - Verilog
Picorv32-IM with exact and approximate SIMD multiplication extensions. The SIMD modules can be accessed with custom RISC-V Instruction to perform dual/quad 8-bit multiplications.
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Jan 28, 2024 - Verilog
Implementation of the 3-stage Sodor Processor using Verilog.
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Dec 13, 2021 - Verilog
Pre and Post Synthesis Simulation of a Design VSDMemSOC
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May 5, 2024 - Verilog
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May 3, 2024 - Verilog
contains my assignment submissions of EE2003 course in 2020
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Dec 26, 2020 - Verilog
An FPGA-based RISC-V SoC to mess around with
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May 12, 2021 - Verilog
Design of a Customizable RISC-V SoC for Clapswitch Application
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Apr 20, 2024 - Verilog