sdram-controller
Here are 9 public repositories matching this topic...
Verilog HDL implementation of SDRAM controller and SDRAM model
-
Updated
Jun 19, 2024 - Verilog
Design Verification of Flash, UART, and SDRAM controller for a 32 bit embedded RISC microprocessor using cocotb.
-
Updated
Oct 15, 2023 - Verilog
SDR SDRAM Controller with Avalon-MM bus; [Bugged, deprecated]
-
Updated
Apr 11, 2022 - Verilog
🛠 A SDRAM controller in Verilog HDL
-
Updated
Mar 21, 2022 - Verilog
SDRAM controller optimized to a memory bandwidth of 316MB/s
-
Updated
Aug 16, 2021 - Verilog
A sample design of Nios with on-board SDRAM for CYC1000 (a low cost Cyclone10 FPGA board)
-
Updated
Jul 8, 2021 - Verilog
Simple SDRAM Controller for DE10-Lite.
-
Updated
Jan 20, 2019 - Verilog
Mitigating Single-Event Upsets in COTS SDRAM using an EDAC SDRAM Controller
-
Updated
Oct 30, 2017 - Verilog
Improve this page
Add a description, image, and links to the sdram-controller topic page so that developers can more easily learn about it.
Add this topic to your repo
To associate your repository with the sdram-controller topic, visit your repo's landing page and select "manage topics."