Source files used in the Embedded Real-Time Systems course at Aarhus University during the spring semester 2018
-
Updated
Jan 7, 2019 - VHDL
Source files used in the Embedded Real-Time Systems course at Aarhus University during the spring semester 2018
Hardware acceleration of edge detection algorithm
Discrete Cosine Transform verification in systemverilog and systemC
An N-bit counter module written in SystemC, VHDL and Verilog
Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)
Add a description, image, and links to the systemc topic page so that developers can more easily learn about it.
To associate your repository with the systemc topic, visit your repo's landing page and select "manage topics."