A proof-of-concept, Rust-inspired, declarative hardware description language optimized for RTL coding
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Updated
Jun 3, 2024 - Rust
A proof-of-concept, Rust-inspired, declarative hardware description language optimized for RTL coding
Format Verilog/SystemVerilog code
Rust library to parse SystemVerilog / Verilog filelists, used in https://github.com/dalance/svlint
Hardware description language with Rust-like syntax
An HDL package manager.
Determines the modules declared and instantiated in a SystemVerilog file
A SystemVerilog Language Server
Veryl: A Modern Hardware Description Language
SystemVerilog parser library fully compliant with IEEE 1800-2017
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