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Diseño de un circuito secuencial con entrada de datos x de 1 bit, una entrada de reset y una entrada de reloj. El sistema es un detector de secuencia que genera una salida z de 1 bit con ‘1’ cuando los últimos cuatro bits recibidos en x son 0101. El circuito se diseña de diversas maneras, cada una de ellas con una descripción en VHDL
This repository contains my custom finite state machine algorithms and their corresponding testbenches, generated using TerosHDL, for robust validation.
Practical application of the hardware description language on the example of the standard player control device. Modeling the behavioral model, verification and obtaining the final result, depicted on the waveform. The control device and verification described with VHDL.