Synthesizable Verilog Source Codes(DUT), Test-bench and Simulation Results.
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Updated
May 10, 2019 - Verilog
Synthesizable Verilog Source Codes(DUT), Test-bench and Simulation Results.
A repository containing the source codes for the Digital Design and Computer Organization Laboratory course (UE18CS2) at PES University.
Implementation of the RISC-V 32 bit Integer and Compressed Instructions in Verilog.
Projeto de uma máquina de lanche desenvolvido como atividade final da disciplina Circuitos Lógicos II.
Digital circuit description to perform multiplication with data_path and control_path using verilog
Hardware Description Language(HDL) based codes using Verilog & VHDL for reference.
Codes performed in labs using Xilinx ISE 14.7
All the fundamental generic verilog modules in one repository. These are fundamentals by my standard, so feel free to suggest more.
Se hace una maquina expendedora a partir de un diagrama de estados para conocer el proceso de venta de 3 gaseosas distintas en las que se tiene en cuenta el sistema de devolución de dinero.
Se hace una recopilación de los sensores utilizados para el proyecto de una casa domotica. Compilado en ISE Design 14.6 y Simulado en ISim.
A small decryption module, written in Verilog, as a university assignment.
This project is to design a processor and memory in the digital system design course at university.
These labs were conducted during our Digital systems elective course were we were instructed to build Verilog code for specific logic design and verify it on Quartus modalism and on the FPGA. Skills developed: writing Verilog code structurally and behaviorally, testing, simulation, writing test benches and using the FPGA
An implementation of 32-bits MIPS Single Cycle Datapath in Verilog HDL.
introduction to Verilog in Integrated Circuit Design And VLSI technology
Verilog Programs
32-bits MIPS Processor with 5-stage pipeline
This is my HDL code page which I started to showcase my coding skills and documenting my work for future reference. I am pursuing my master's at Texas A&M University (2019-21). I am looking forward to be a verification engineer. If you have any doubts you are welcomed to email me @ arunraja08@gmail.com
Verilog Implementation of Run Length Encoding for RGB Image Compression
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