NSCSCC2022龙芯杯个人赛，MIPS32，59MHz经典五级流水线架构，易于初学者阅读（计算机组成原理，自己动手写CPU）
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Mar 19, 2024 - VHDL
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verilog-project
Here are 8 public repositories matching this topic...
Image Processing Toolbox in Verilog using Basys3 FPGA
python
fpga
ram
pixel
vhdl
image-processing
python3
verilog
convolution
vivado
motion-blur
verilog-hdl
basys3
digital-systems
hsync
basys
basys-board
coe
verilog-project
basys3-fpga
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Sep 19, 2023 - VHDL
Course project for Computer Design and Practice at HIT.
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May 17, 2020 - VHDL
A sprite clicker game, similar to that of the popular game "Osu". The game can be implented using a vanilla FPro system for the NEXYS A7 fpga board. The game utilitizes the PS2 protocol to allow for mouse input and the boards VGA adapter to display visuals on screen.
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May 7, 2020 - VHDL
Proyecto desarrollado para la asignatura de Laboratorio de Electrónica Digital
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Feb 15, 2019 - VHDL
RISC processor done in verilog hdl for FPGA
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Jul 13, 2018 - VHDL
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Jul 11, 2018 - VHDL
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