vhdl
Here are 26 public repositories matching this topic...
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Dec 11, 2017 - SystemVerilog
This project simules the basic functions of PIC16F84a.
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May 3, 2018 - SystemVerilog
Rešenja zadataka sa vežbi iz predmeta "Projektovanje namenskih računarskih struktura 2"
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Apr 9, 2019 - SystemVerilog
VHDL implementation of VGA controller. Implemented on Zybo Zynq-7000 board which uses switches to change output color.
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May 12, 2019 - SystemVerilog
A simple arithmetic logic unit (ALU) with System verilog
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Aug 21, 2020 - SystemVerilog
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Feb 18, 2021 - SystemVerilog
My CMPE 691 491 Repo, I don't want to lose my school work code, so I back it up to here.
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May 14, 2021 - SystemVerilog
Implements instruction split, opcode and alucontrol codes generation.
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Jan 4, 2022 - SystemVerilog
System Verilog BootCamp
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Jan 21, 2022 - SystemVerilog
Vector ASIP for the application of filters to an image 🖼️
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May 19, 2022 - SystemVerilog
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Oct 1, 2023 - SystemVerilog
An 8-bit counter that counts from 0 to 255 when it is enabled and parallelly loaded. Structural approach is used here and treated as a black box and is verified using OOP based testbench.
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Oct 6, 2023 - SystemVerilog
A single SystemVerilog package with both classes of half as well as full adder is created and tested using the testbench
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Oct 13, 2023 - SystemVerilog
Counter that counts even numbers is created using a chain of eight D flip-flops. An OOP-based test bench and a package is developed to verify the counter's functionality as a black box and compare its output against the expected even number sequence. The design was implemented in two approaches i.e, asynchronous and synchronous structures.
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Oct 13, 2023 - SystemVerilog
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