Using Vivado HLS to create floating point IP, used to accelerate a Zynq system. Multiple engines are instantiated.
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Updated
Jan 21, 2018 - VHDL
Using Vivado HLS to create floating point IP, used to accelerate a Zynq system. Multiple engines are instantiated.
A fast and efficient implementation of a SHA256 cracker
Implementation in VHDL of an HW component capable of recalibrating the contrast of an image stored in an external memory, using a histogram equalization algorithm.
Implementation of a (soft) coprocessor for the computation of a 16 bit LFSR.
Advanced Computer Architecture at EPFL.
University of Pittsburgh ECE 1195
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