Designinig a Pipeline in-order 5 stage RISC-V core RV32I-MAF
-
Updated
May 9, 2022 - SystemVerilog
Designinig a Pipeline in-order 5 stage RISC-V core RV32I-MAF
Spiking Neural Network Accelerator
"Mastering SystemVerilog: From Fundamentals to Advanced Programming Techniques"
SystemVerilog verification of I2C interface
A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.
Add a description, image, and links to the vlsi-design topic page so that developers can more easily learn about it.
To associate your repository with the vlsi-design topic, visit your repo's landing page and select "manage topics."