Design rule checker for VLSI layouts
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Updated
Jun 21, 2024 - C++
Design rule checker for VLSI layouts
Standard Cell Library based Memory Compiler using FF/Latch cells
Deep learning toolkit-enabled VLSI placement
This is a SpyDrNet Plugin for a physical design related transformations
Standard cell placement (global and detailed) tool based on modified algorithm “simulated annealing”
Micro-Framework for FPGA / VLSI Design Flow in Python
2 Week digital VLSI SoC design and planning workshop with complete RTL2GDSII flow organized by VSD in collaboration with NASSCOM (Advanced Physical Design using OpenLANE /Sky130)
Entries for the 2023 5th National College Student Integrated Circuit EDA Elite Challenge. SoC chip physical layout static IR drop prediction project based on methods such as image processing and NLP unsupervised learning.
This repository contains python code snippets that implement several algorithms for automating the VLSI Physical Design process. This is based on the learnings from the course - EE5333W (Introduction to Physical Design Automation) at IITM.
This repository is dedicated to VLSI ASIC Design Flow using open-source tools! Here, we embark on a journey that starts with specifications, RTL DV, Synthesis, Physical Design, Signoff and Finally Tape-It-Out
The course "NTHU VLSI System Design and Implementation"
5 Day TCL begginer to advanced training workshop by VSD
VLSI CAD Algorithm Visualizations implemented as Java Applications
A High-performance Timing Analysis Tool for VLSI Systems
Dr. CU, VLSI Detailed Routing Tool Developed by CUHK
Coursework of NTHU CS613500 VLSI Physical Design Automation
Some simple examples for the Magic VLSI physical chip layout tool using Google Skywater130 PDK.
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