A High-performance Timing Analysis Tool for VLSI Systems
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Updated
May 26, 2023 - Verilog
A High-performance Timing Analysis Tool for VLSI Systems
phoeniX RISC-V Processor
Standard Cell Library based Memory Compiler using FF/Latch cells
DATC RDF
FAN (fan-out-oriented) ATPG (Automatic Test Pattern Generation) and Fault Simulation command line tool
cdsAsync: An Asynchronous VLSI Toolset & Schematic Library
Dadda multiplier(8*8, 16*16, 32*32) in Verilog HDL.
All the projects and assignments done as part of VLSI course.
work done as part of VLSI Design practice course
IEEE DATC Robust Design Flow 2021.
Projects and labs from the courses dictated in https://www.coursera.org/specializations/fpga-design. Projects are sometimes simulated, and implemented in either a MAX10-Lite or an Arrow MAX1000 board.-
Computer Architecture -VLSI -Verilog Codes-Xilinx-Irsim
generic NetList data structure for VLSI
This project give overview of RTL to GDSII of universal shift register using OpenLane and Skywater130 PDK. OpenLane is an automated open-source EDA tool which gives RTL to GDSII flow.
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