A coocbook of HDL (primarily Verilog) modules
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Updated
Apr 24, 2017 - Verilog
A coocbook of HDL (primarily Verilog) modules
中国科学院大学 计算机组成原理FPGA实验课程 - "Five projects to better understand key principles of computer systems", UCAS Spring 2017 Session
This is a simple project that shows how to multiply two 3x3 matrixes in Verilog.
Bare metal (without embedded OS) DC motor speed control system
Two Verilog SPI module implementations (hard and soft) with advanced options and AXI Full Interface
way to use xapp1052 with new version of PCIe IP core(AXI bus)
FPGA Tetris written in Verilog
FPGA based single player game
Quick Verilog Module Isolator - Isolates a design for testing.
Verilog code that could run on Nexys3 (Spartan-6)
Open-source CSI-2 receiver for Xilinx UltraScale parts
FPGA Messbauer hardware (generator, emulation of signal from gamma-source registered and amplified
SPI bus slave and flip-flop register memory map implemented in Verilog 2001 for FPGAs
verilog modules
SPI module for Nexys 4 Artix-7 FPGA Trainer Board
Minimal DVI / HDMI Framebuffer
RISC based 8-bits five stage pipelined processor, operating at 585 MHz clock frequency with 19 I/O pins and 28 instructions having 5 Addressing formats. Tested on Xilinx Artix-7 FPGA.
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