A single cycle CPU running MIPS instructions on Xilinx FPGA
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Updated
Aug 27, 2017 - Verilog
A single cycle CPU running MIPS instructions on Xilinx FPGA
Simple CPU Design in Verilog with MIPS-like Architecture, featuring Branch Prediction and Interrupt Control.
Implementation of a model of pipelined MIPS processor in Verilog
In the repository I have implemented a ALU with Finite State machine with VHDL and Xilinx ISE 14.7 application. Also a BCD to seven segment have been implemented for input and output digits.
Running your application from DDR memory & BPI flash using SREC bootloader
These are VHDL codes that I wrote as a part of our Computer Architecture Course in the 4th Semester.
🖼✏️ My first baby steps into the world of image processing
Design and Implementation of Arithmetic Logic Unit Capable of Calculating Z=1/4(A X B)+1
This project aims to test how fast you can respond after seeing a visual stimulus or rather hand-eye coordination.
saving lab experiments in this repo, specific to MAKAUT ECE-2021 7th SEM(old syllabus)
UART implementation using Verilog HDL
This is Amirkabir University Logic Circuit Design final project 2022
This repository contains VHDL codes for a 16 bit binary square root computer module.
This rep contains neighbour's cpu. Single-cycle / Multi-cycle CPU implementation in vhdl using ISE Xiling
VHDL Verilog / Clock on Spartan3 / 2014 University of Seoul
saving lab experiments in this repo, specific to MAKAUT ECE-2021 7th SEM(old syllabus)
Small project to track things with a waterproof sonar sensor
To implement the elevator controller, we used Verilog as HDL. The focus of our project was the implementation and verification of a controller for a basic elevator functionality. We also proposed a methodology that utilizes the SCAN algorithm to enhance the efficiency and reliability of the controller.
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