16-bit RISC Processor using Verilog HDL

📌 Overview

This project implements a 16-bit Reduced Instruction Set Computer (RISC) Processor using Verilog HDL. The processor follows a modular architecture, where each hardware component is designed and verified independently before system integration.

The design was developed and simulated using Xilinx Vivado 2017.2, demonstrating the working of fundamental processor components including the ALU, Register File, Program Counter, Control Unit, and Instruction Decoder.

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✨ Features

• 16-bit RISC Processor architecture
• Modular Verilog HDL implementation
• Arithmetic Logic Unit (ALU)
• Register File
• Program Counter
• Instruction Decoder
• Control Unit
• RAM Interface
• Functional simulation using Vivado
• RTL schematic generation

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🛠️ Tools & Technologies

• Verilog HDL
• Xilinx Vivado 2017.2
• Digital Logic Design

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📂 Project Structure

16-bit-RISC-Processor/
│
├── Source_Code/
│   ├── alu.v
│   ├── ctrl_unit.v
│   ├── fake_ram.v
│   ├── inst_dec.v
│   ├── pc_unit.v
│   └── reg_file.v
│
├── Testbench/
│
├── Images/
│   ├── RTL_Schematic.png
│   └── Simulation.png
│
├── Documentation/
│   └── 16-bit_RISC_Processor_Report.pdf
│
└── README.md

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🧩 Processor Modules

• Arithmetic Logic Unit (ALU)
• Control Unit
• Instruction Decoder
• Register File
• Program Counter
• Fake RAM Module

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🏗 RTL Schematic

The RTL schematic generated by Xilinx Vivado illustrates the hardware architecture and interconnection of the processor modules.

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📊 Simulation Result

The simulation waveform validates the functionality of the processor by demonstrating correct signal transitions and module interactions.

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▶️ How to Run

1. Open Xilinx Vivado 2017.2.
2. Create a new Verilog project.
3. Add all files from the Source_Code directory.
4. Add the testbench files from Testbench.
5. Run Behavioral Simulation.
6. Verify the output waveform.
7. Open Elaborated Design to view the RTL schematic.

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📚 Learning Outcomes

• Verilog HDL Programming
• Processor Architecture
• RTL Design
• Digital System Design
• Hardware Module Integration
• Testbench Development
• Functional Simulation
• RTL Analysis using Vivado

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🚀 Future Improvements

• Instruction Memory
• Data Memory
• Pipeline Architecture
• Hazard Detection
• Forwarding Unit
• FPGA Implementation

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👨‍💻 Author

Dhruv Balsara

Electronics & Telecommunication Engineering Student
Dwarkadas J. Sanghvi College of Engineering (DJSCE), Mumbai

• GitHub: https://github.com/DhruvBalsara
• LinkedIn: https://www.linkedin.com/in/dhruvbalsara-djsce