add AArch64 support: master issue #1569
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In api/samples/CMakeLists.txt I noticed that bbbuf.c is the only sample listed as not yet ported from AArch32 to AArch64. However #1982 modifies bbbuf.c to use drx_buf, to which AArch64 support was added (not by me). Would someone with an AArch64 setup be able to verify it works and modify CMakelists.txt as appropriate? |
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bbbuf was enabled on AArch64 a while ago by fa7e5c5 |
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@toshipiazza |
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Unfortunately we didn't have auto-links for partial commits so I'm pasting in the many commits contributing to the port so far: 2017-07-20 c908cdd i#1569 AArch64: Make encodings easier to specify. (#2549) |
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Full list of AArch64-tagged open issues: link More important issues grouped and roughly prioritised: #1698 ldrex..strex pair constraints challenge instrumentation and even core operation
#2626 Finish AArch64 encoder/decoder
#2425 Node.js does not run under DynamoRIO on AArch64
#2417 Fix flaky tests on AArch64
#2065 several code emitting and patching routines fail to sync the hardware icache
#2502 races in ARM lockless data structure reads
#2358 CRASH on AArch64 when many signals are received
#2154 BUILD: Building for Android AARCH64 on Linux
#1621 clean call optimizations on AArch64: out-of-line, analyze and reduce cxt sw, inline
xxxxx Port Dr Memory to AArch64
#2210 AArchXX clean calls handle far too few use cases, blocking tool development
#2072 drreg-test fails with non-default stolen register
#1936 DynamoRIO fails to run trivial "clone" example on ARM
#2390 Reduce overhead of indirect branch on AArch64
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Instructions that take logical immediates are not encoded with shifts. Issue: #1569 Change-Id: Ib85757d2bdb6c05008d14be47f4d706a85f4f58f
Instructions that take logical immediates are not encoded with shifts. Issue: #1569
Add decoding and encoding for system registers TPIDRRO_EL0 and CNTVCT_EL0. Issue: #1569
Enables the diagnostic option -steal_reg_at_reset for AArch64, generalizing the existing ARM code. Switches -reset_at_fragment_count to work in release build by using the sum of the release stats num_bbs and num_traces. Adds a release-build syslog for an informational notification when any reset occurs. Adds a test of -steal_reg_at_reset. Issue: #1569
…5045) This patch incorporated changes from PR #2442 that implemented the initial version of trace support for AArch64. This patch also fixed some corner cases not considered in PR #2442 where the assumption was incorrect and caused the program to crash. Trace support is not yet enabled by default, but can be enabled with "-enable_traces". This commit introduces internal control flow by adding a trace_exit_label in fixup_indirect_trace_exit, which might break code that assumes linear control flow (such as translate.c). Either special support is needed for this trace_exit_label or alternative schemes should be used that has a linear control. Some complexities in this commit can be removed once we have #5062 implemented and decode_fragment eliminated. Co-authored-by: Kevin Zhou <Kevin.Zhou@arm.com> Issues: #1569, #2974
This patch reads from the ID_AA64ISAR0_EL1 features register and sets the following if supported: FEATURE_AES FEATURE_PMULL FEATURE_SHA1 FEATURE_SHA256 FEATURE_SHA512 FEATURE_CRC32 FEATURE_LSE FEATURE_RDM FEATURE_SM3 FEATURE_SM4 FEATURE_DotProd FEATURE_FHM FEATURE_FlagM2 FEATURE_RNG FEATURE_SHA3 FEATURE_FlagM Example output in logfile: - - - snip Processor features: ID_AA64ISAR0_EL1 = 0x0000000000011120 Processor has FEATURE_AES Processor has FEATURE_PMULL Processor has FEATURE_SHA1 Processor has FEATURE_SHA256 Processor has FEATURE_CRC32 - - - snip ID_AA64ISAR1_EL1 and ID_AA64PFR0_EL1 are also read. The features for these will be implemented in the next patch. Issues: #5474, #1569
This patch reads from the ID_AA64ISAR0_EL1 features register and sets the following if supported: FEATURE_AES FEATURE_PMULL FEATURE_SHA1 FEATURE_SHA256 FEATURE_SHA512 FEATURE_CRC32 FEATURE_LSE FEATURE_RDM FEATURE_SM3 FEATURE_SM4 FEATURE_DotProd FEATURE_FHM FEATURE_FlagM2 FEATURE_RNG FEATURE_SHA3 FEATURE_FlagM Example output in logfile: - - - snip Processor features: ID_AA64ISAR0_EL1 = 0x0000000000011120 Processor has FEATURE_AES Processor has FEATURE_PMULL Processor has FEATURE_SHA1 Processor has FEATURE_SHA256 Processor has FEATURE_CRC32 - - - snip ID_AA64ISAR1_EL1 and ID_AA64PFR0_EL1 are also read. The features for these will be implemented in the next patch. Issues: #5474, #1569
This patch implements the codec side of the AArch64 FEATURE_ support
patch, PR5491. A feature name field is added to each opcode in
codec_*.txt files which is used to generate feature checks in the
encoder, e.g.
switch (instr->opcode) {
case OP_cas:
# if !defined(DR_HOST_NOT_TARGET) && !defined(STANDALONE_DECODER)
if (!proc_has_feature(FEATURE_LSE))
return ENCFAIL;
# endif
enc = encode_opndsgen_08a07c00_001f03ff(pc, instr,..., di);
if (enc != ENCFAIL)
return enc;
Issues: #5475, #1569, #2626
This patch implements the codec side of the AArch64 FEATURE_ support patch, PR #5491. A feature name field is added to each opcode in codec_*.txt files which is used to generate feature checks in the encoder, e.g. switch (instr->opcode) { case OP_cas: # if !defined(DR_HOST_NOT_TARGET) && !defined(STANDALONE_DECODER) if (!proc_has_feature(FEATURE_LSE)) return ENCFAIL; # endif enc = encode_opndsgen_08a07c00_001f03ff(pc, instr,..., di); if (enc != ENCFAIL) return enc; Issues: #5475, #1569, #2626
GCC11 has stricter requirements for uninitialised variables in -O3 mode Issue: #1569
This patch adds some code to the runsuite wrapper to print critical information about the runner such as os, kernal version and cpu. Currently this block looks like: =========== System info =========== OS: Ubuntu 20.04.6 LTS Kernel Version: 5.15.0-1043-aws CPU: Neoverse V1 Clang version: Ubuntu clang version 12.0.0-3ubuntu1~20.04.5 GCC version: gcc (Ubuntu 11.4.0-2ubuntu1~20.04) 11.4.0 Features: fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics... =================================== and is only shown during AArch64 runs, just before the results. issue: #1569 Change-Id: Ic68d1987b036ec853f5ef1c232bb96ce8d652663
This patch adds some code to the runsuite wrapper to print critical information about the runner such as os, kernel version and cpu. Currently this block looks like: ``` =========== System info =========== OS: Ubuntu 20.04.6 LTS Kernel Version: 5.15.0-1043-aws CPU: Neoverse V1 Clang version: Ubuntu clang version 12.0.0-3ubuntu1~20.04.5 GCC version: gcc (Ubuntu 11.4.0-2ubuntu1~20.04) 11.4.0 Features: fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics... =================================== ``` and is only shown during AArch64 runs, just before the results. issue: #1569
1. For RISCV64, conditional branch instruction of 'C' extension may not reach after adding clean call. So like X86, we add support to detect and convert compressed cbr to longer version. 2. For AARCH64 and RISCV64, a cbr may use the stolen reg and can not be mangled later as it is meta. So we check whether a cbr uses the stolen reg and replace it with a scratch reg. Now cbr works for AARCH64 and RISCV64. Still not work for ARM32 because of some bugs unrelated to cbr sample. Issue: DynamoRIO#1569,DynamoRIO#3544
1. For RISCV64, conditional branch instruction of 'C' extension may not reach after adding clean call. So like X86, we add support to detect and convert compressed cbr to longer version. 2. For AARCH64 and RISCV64, a cbr may use the stolen reg and can not be mangled later as it is meta. So we check whether a cbr uses the stolen reg and replace it with a scratch reg. Now cbr works for AARCH64 and RISCV64. Still not work for ARM32 because of some bugs unrelated to cbr sample. Issue: DynamoRIO#1569, DynamoRIO#3544
1. For RISCV64, conditional branch instruction of 'C' extension may not reach after adding clean call. So like X86, we add support to detect and convert compressed cbr to longer version. 2. For AARCH64 and RISCV64, a cbr may use the stolen reg and can not be mangled later as it is meta. So we check whether a cbr uses the stolen reg and replace it with a scratch reg. Now cbr works for AARCH64 and RISCV64. Still not work for ARM32 because of some bugs unrelated to cbr sample. Issue: DynamoRIO#1569, DynamoRIO#3544
1. For RISCV64, conditional branch instruction of 'C' extension may not reach after adding clean call. So like X86, we add support to detect and convert compressed cbr to longer version. 2. For AARCH64 and RISCV64, a cbr may use the stolen reg and can not be mangled later as it is meta. So we check whether a cbr uses the stolen reg and replace it with a scratch reg. Now cbr works for AARCH64 and RISCV64. Still not work for ARM32 because of some bugs unrelated to cbr sample. Issue: DynamoRIO#1569, DynamoRIO#3544
Split from issue #1551 as our initial focus is just AArch32.
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