AI accelerators are the engines behind modern machine learning — the GPUs, TPUs, NPUs, and custom ASICs that make training and inference practical at scale. Building and programming them is a deeply interdisciplinary craft that spans deep learning, computer architecture, compilers, GPU programming, RTL design, and physical implementation.

This list is a curated, opinionated map of that landscape. It favors canonical papers and widely adopted open-source projects over exhaustive coverage. Whether you are an undergraduate taking your first architecture course, a PhD student researching dataflow architectures, or an engineer optimizing kernels at a frontier lab, the goal is to give you the best resource for each topic — and a clear path through the rest.

• AI Foundations
  • AI Fundamentals
  • Deep Learning
  • Transformers & LLMs
  • Diffusion Models
  • Vision Models
  • Reinforcement Learning
• AI Inference
  • Quantization
  • KV Cache
  • Speculative Decoding
  • Prefix Caching
  • Continuous Batching
  • Mixture of Experts
  • Sparsity & Pruning
  • Scheduling
  • Memory Optimization
  • Serving Systems
• GPU Programming
  • CUDA
  • Triton
  • ROCm
  • Metal
• AI Kernels
  • GEMM
  • FlashAttention
  • PagedAttention
  • Normalization & Softmax
  • RoPE & Positional Encodings
  • Fused Operators
  • Kernel Optimization Guides
• Runtime Systems
• Compilers
• Computer Architecture
  • Foundations
  • Memory Systems & Cache
  • Interconnect & NoC
  • Dataflow & Systolic Arrays
  • SIMD, SIMT & Tensor Cores
  • Processing-in-Memory
• AI Accelerator Architecture
  • GPUs
  • TPUs & Systolic ASICs
  • NPUs & Edge AI
  • FPGA & Reconfigurable
  • RISC-V for AI
• Simulators & Modeling
• Chip Design
  • Blogs & Newsletters
  • YouTube Channels
  • Interactive & Visual
• RTL Design
• Design Verification
• Physical Design
• University Courses

Understanding the workloads is the prerequisite for accelerating them. This section covers the models that drive accelerator design.

• Deep Learning — Goodfellow, Bengio, and Courville's foundational textbook, freely available online.
• Dive into Deep Learning (D2L) — Interactive book with runnable code in PyTorch, JAX, and TensorFlow.
• Neural Networks and Deep Learning — Michael Nielsen's intuitive introduction to the core ideas.
• The Matrix Calculus You Need For Deep Learning — Parr and Howard's practical primer on the math behind backprop.

• ImageNet Classification with Deep CNNs (AlexNet) — The 2012 paper that ignited the deep learning era.
• Deep Residual Learning (ResNet) — Residual connections that enabled very deep networks.
• Batch Normalization — Normalizing activations to accelerate and stabilize training.
• Adam: A Method for Stochastic Optimization — The default optimizer for most deep learning workloads.
• The Bitter Lesson — Rich Sutton's essay on why general methods that scale with compute win.

• Attention Is All You Need — The Transformer architecture; the single most important paper for modern AI accelerators.
• The Illustrated Transformer — Jay Alammar's visual walkthrough of the architecture.
• The Annotated Transformer — Harvard NLP's line-by-line implementation in PyTorch.
• BERT — Bidirectional pretraining that reshaped NLP.
• GPT-2: Language Models are Unsupervised Multitask Learners — Scaling generative pretraining toward zero-shot task transfer.
• GPT-3: Language Models are Few-Shot Learners — Demonstrated emergent in-context learning at scale.
• T5: Exploring the Limits of Transfer Learning — The unified text-to-text framing of NLP tasks.
• Scaling Laws for Neural Language Models — Kaplan et al.'s power-law relationships between compute, data, and loss.
• Training Compute-Optimal LLMs (Chinchilla) — The compute-optimal scaling result that reset training recipes.
• LLaMA — Efficient open foundation models that catalyzed the open LLM ecosystem.
• Mistral 7B — Grouped-query and sliding-window attention for efficient inference.
• DeepSeek-V3 — A 671B fine-grained MoE model trained efficiently with FP8 and MLA.
• DeepSeek-R1 — Eliciting strong reasoning through large-scale reinforcement learning.
• nanoGPT — Karpathy's minimal, hackable GPT training and inference codebase.
• The Ultra-Scale Playbook — Hugging Face's practical guide to training LLMs on GPU clusters (data, tensor, pipeline, and expert parallelism).
• The Smol Training Playbook — Hugging Face's end-to-end field guide to building world-class LLMs.

• Denoising Diffusion Probabilistic Models (DDPM) — The paper that made diffusion models practical.
• High-Resolution Image Synthesis with Latent Diffusion (Stable Diffusion) — Diffusion in latent space for efficient, high-quality generation.
• Classifier-Free Diffusion Guidance — The guidance technique underlying modern text-to-image models.
• Scalable Diffusion Models with Transformers (DiT) — Replacing the U-Net backbone with transformers.
• What are Diffusion Models? — Lilian Weng's comprehensive tutorial.

• An Image is Worth 16x16 Words (ViT) — Applying pure transformers to image classification.
• Segment Anything (SAM) — A promptable foundation model for image segmentation.
• CLIP: Learning Transferable Visual Models — Contrastive language-image pretraining that bridges vision and text.
• YOLO — Real-time object detection as a single regression problem.

• Reinforcement Learning: An Introduction — Sutton and Barto's canonical textbook, freely available.
• Playing Atari with Deep RL (DQN) — Deep Q-networks that learned to play from pixels.
• Proximal Policy Optimization (PPO) — The workhorse policy-gradient algorithm, now central to RLHF.
• Spinning Up in Deep RL — OpenAI's educational resource with clean implementations.

Inference — not training — dominates the lifetime compute of a deployed model. This section covers the algorithms and systems that make LLM serving fast and cheap.

• TurboQuant — Online vector quantization with near-optimal distortion, delivering large KV cache memory savings and attention speedups.
• LLM.int8() — 8-bit matrix multiplication for transformers with outlier handling.
• GPTQ — Accurate post-training quantization to 3–4 bits.
• AWQ: Activation-aware Weight Quantization — Protecting salient weights for low-bit LLM inference.
• SmoothQuant — Migrating quantization difficulty from activations to weights.
• QLoRA — 4-bit NormalFloat quantization enabling fine-tuning on a single GPU.
• FP8 Formats for Deep Learning — The NVIDIA/Arm/Intel proposal behind Hopper's FP8 support.
• A Survey of Quantization Methods — Comprehensive survey of efficient neural network inference.

• Efficient Memory Management for LLM Serving (PagedAttention) — The vLLM paper; treats KV cache like OS virtual memory.
• Multi-Query Attention — Sharing keys and values across heads to shrink the KV cache.
• GQA: Grouped-Query Attention — Interpolating between multi-head and multi-query attention.
• H2O: Heavy-Hitter Oracle — KV cache eviction based on attention scores.
• KVQuant — Ultra-low-bit KV cache quantization for long context.
• DeepSeek-V2 (Multi-head Latent Attention) — Low-rank KV compression that dramatically cuts cache size.

• Fast Inference from Transformers via Speculative Decoding — The original speculative decoding paper from Google.
• Accelerating LLM Decoding with Speculative Sampling — DeepMind's concurrent formulation.
• Medusa — Multiple decoding heads for parallel speculation without a draft model.
• EAGLE — Speculative sampling at the feature level for higher acceptance rates.
• Lookahead Decoding — Breaking the sequential dependency without a draft model.

• SGLang: Efficient Execution with RadixAttention — Automatic KV reuse across requests via a radix tree.
• Prompt Cache — Modular attention reuse for recurring text segments.
• ChunkAttention — Prefix-aware KV cache with a shared prefix trie.

• Orca: A Distributed Serving System for Transformers — Introduced iteration-level (continuous) batching at OSDI '22.
• How Continuous Batching Enables 23x Throughput — Anyscale's widely cited explainer.
• DistServe — Disaggregating prefill and decode for goodput-optimal serving.
• Sarathi-Serve — Chunked prefills that balance throughput and latency.

• Outrageously Large Neural Networks (Sparsely-Gated MoE) — Shazeer et al.'s foundational MoE layer.
• Switch Transformers — Simplified routing scaling to trillion-parameter models.
• GShard — Scaling MoE with automatic sharding.
• Mixtral of Experts — A strong open sparse MoE model.
• MegaBlocks — Block-sparse GPU kernels for dropless MoE training.
• DeepSeek-V3 — Fine-grained MoE with auxiliary-loss-free load balancing at scale.

• The Lottery Ticket Hypothesis — Sparse subnetworks that train to full accuracy.
• Learning both Weights and Connections (Deep Compression) — Han et al.'s pruning + quantization + Huffman coding pipeline.
• SparseGPT — One-shot pruning of massive language models.
• Wanda — Pruning by weights and activations, no retraining required.
• Accelerating Sparse DNNs with 2:4 Sparsity — NVIDIA's structured sparsity for Tensor Cores.

• FastServe — Preemptive scheduling to minimize job completion time.
• Llumnix — Dynamic request rescheduling across serving instances.
• Splitwise — Phase-splitting prefill and decode across heterogeneous hardware.

• ZeRO: Memory Optimizations Toward Training Trillion-Parameter Models — Partitioning optimizer state, gradients, and parameters.
• FlexGen — High-throughput generative inference with offloading on a single GPU.
• Reducing Activation Recomputation (Selective Checkpointing) — Trading compute for memory in large transformers.
• InfiniGen — Dynamic KV cache management with speculative prefetching.

• DeepSpeed-Inference — Multi-GPU inference optimizations for transformer models.
• AlpaServe — Statistical multiplexing with model parallelism for serving.
• Efficiently Scaling Transformer Inference — Google's partitioning analysis for TPU inference at scale.
• Mooncake — KVCache-centric disaggregated architecture behind Kimi.

The lingua franca of accelerator programming. This section covers the major parallel programming models.

• CUDA C++ Programming Guide — The authoritative reference from NVIDIA.
• CUDA C++ Best Practices Guide — Performance optimization guidance straight from the source.
• Programming Massively Parallel Processors — Hwu, Kirk, and El Hajj's definitive CUDA textbook (PMPP).
• How to Optimize a CUDA Matmul Kernel — Simon Boehm's step-by-step walk to near-cuBLAS performance.
• GPU MODE Lectures — Community lecture series and code on writing fast GPU kernels.
• CUTLASS — NVIDIA's CUDA templates for high-performance GEMM and beyond.

• Triton: An Intermediate Language and Compiler — The original paper by Philippe Tillet.
• Triton — OpenAI's Python DSL for writing efficient GPU kernels.
• Triton Tutorials — Official tutorials from vector-add to fused attention.

• ROCm Documentation — AMD's open compute platform for GPU acceleration.
• HIP Programming Guide — CUDA-portable C++ runtime API for AMD and NVIDIA GPUs.
• Composable Kernel — AMD's performance library for GEMM and fused operators.

• Metal Performance Shaders — Apple's optimized GPU compute primitives.
• MLX — Apple's NumPy-like array framework for Apple silicon.
• Metal Shading Language Specification — The reference for writing Metal compute kernels.

The hand-tuned building blocks where most accelerator FLOPs are spent.

• Anatomy of High-Performance Matrix Multiplication — Goto and van de Geijn's classic on blocking for the memory hierarchy.
• CUTLASS — Composable GEMM templates that expose Tensor Core performance.
• How To Optimize GEMM — A pedagogical, step-by-step optimization of matrix multiply.
• CuTe Layout Algebra — CUTLASS 3.x's abstraction for tensor layouts and tiling.

• FlashAttention — IO-aware exact attention that avoids materializing the score matrix.
• FlashAttention-2 — Better parallelism and work partitioning for near-peak throughput.
• FlashAttention-3 — Exploiting Hopper asynchrony and FP8 for the H100.
• flash-attention — The reference implementation from Tri Dao's lab.
• FlashInfer — A kernel library for LLM serving with attention variants.

• PagedAttention (vLLM) — Non-contiguous KV cache blocks to eliminate memory fragmentation.
• vLLM Kernels — Production PagedAttention and quantized kernel implementations.

• Root Mean Square Layer Normalization — RMSNorm, the normalization used in most modern LLMs.
• Layer Normalization — Ba, Kiros, and Hinton's original formulation.
• Online Normalizer Calculation for Softmax — The single-pass softmax trick underlying FlashAttention.

• RoFormer: Rotary Position Embedding — RoPE, the positional encoding used across modern LLMs.
• YaRN — Efficient context-window extension for RoPE models.
• ALiBi — Attention with linear biases for length extrapolation.

• Automatic Kernel Fusion (TVM) — Operator fusion as part of an end-to-end DL compiler.
• Liger Kernel — Fused Triton kernels for efficient LLM training.
• NVIDIA Apex — Fused Adam, LayerNorm, and other mixed-precision training kernels.

• GPU Performance Background — NVIDIA's model for reasoning about arithmetic intensity and roofline.
• Making Deep Learning Go Brrrr From First Principles — Horace He on compute, memory, and overhead bound regimes.
• What Every Programmer Should Know About Memory — Ulrich Drepper's essential treatment of the memory hierarchy.

Frameworks that take a trained model and run it efficiently on real hardware.

• vLLM — High-throughput LLM serving engine built around PagedAttention.
• TensorRT-LLM — NVIDIA's optimized LLM inference library with in-flight batching.
• SGLang — Fast serving with RadixAttention and a co-designed frontend language.
• MLC-LLM — Universal LLM deployment across GPUs, phones, and browsers via TVM.
• llama.cpp — Portable C/C++ inference with aggressive quantization (GGUF).
• Ollama — Simple local model running built on llama.cpp.
• TensorRT — NVIDIA's high-performance deep learning inference SDK.
• ONNX Runtime — Cross-platform inference and training accelerator.
• Apache TVM — End-to-end deep learning compiler stack (see Compilers).
• tinygrad — A minimalist framework with a lazy, fused execution model.
• ExecuTorch — PyTorch's on-device inference runtime for mobile and edge.
• OpenXLA / XLA — The domain-specific compiler behind JAX and TensorFlow.
• DeepSpeed — Microsoft's training and inference optimization library.
• LMDeploy — Toolkit for compressing and serving LLMs.
• Text Generation Inference (TGI) — Hugging Face's production serving toolkit.

The bridge between ML frameworks and silicon.

• MLIR — Multi-Level IR; the shared compiler infrastructure behind most modern AI stacks.
• MLIR: Scaling Compiler Infrastructure (paper) — Lattner et al.'s introduction to the framework.
• LLVM — The compiler infrastructure that underpins essentially everything below.
• TVM: An Automated End-to-End Optimizing Compiler — The Apache TVM paper.
• IREE — An MLIR-based end-to-end compiler and runtime for ML models.
• OpenXLA — XLA and StableHLO, the compiler ecosystem for JAX/TF/PyTorch.
• Triton Compiler — Lowers a Python tile DSL to fast GPU code through MLIR.
• torch.compile / TorchInductor — PyTorch 2.x's graph capture and Triton-based codegen.
• Glow — A graph-lowering compiler for neural network hardware accelerators.
• Mojo — Modular's Python-superset language for AI systems programming.
• Halide — Decoupling algorithm from schedule for high-performance tensor and imaging code.
• The Deep Learning Compiler: A Comprehensive Survey — A map of the DL compiler landscape.

The foundation every accelerator is built on.

• Computer Architecture: A Quantitative Approach — Hennessy and Patterson's definitive graduate text.
• Computer Organization and Design — Patterson and Hennessy's undergraduate RISC-V edition.
• Processor Microarchitecture: An Implementation Perspective — González, Latorre, and Magklis's concise tour of how out-of-order cores are actually built.
• A New Golden Age for Computer Architecture — Hennessy and Patterson's Turing Award lecture on domain-specific architectures.
• Onur Mutlu's Computer Architecture Lectures — ETH Zürich's comprehensive, freely available course.

• What Every Programmer Should Know About Memory — The reference on caches, DRAM, and memory-aware programming.
• High Bandwidth Memory (HBM) Standard — The JEDEC standard powering modern accelerator memory.
• DRAMSim3 — A cycle-accurate DRAM simulator for architecture research.
• Ramulator 2.0 — A fast, extensible DRAM simulator for modern memory standards.

• Principles and Practices of Interconnection Networks — Dally and Towles's definitive text.
• NVLink and NVSwitch — NVIDIA's high-bandwidth GPU-to-GPU interconnect.
• BookSim2 — A cycle-accurate interconnection network simulator.
• Ultra Ethernet Consortium — An emerging open standard for scale-out AI fabrics.

• Why Systolic Architectures? — H. T. Kung and Charles Leiserson's foundational 1982 work.
• Eyeriss: Energy-Efficient Reconfigurable Accelerator — Chen et al.'s influential dataflow accelerator and taxonomy.
• Efficient Processing of Deep Neural Networks — Sze, Chen, Yang, and Emer's essential survey book.
• Timeloop / Accelergy — Infrastructure for evaluating and mapping DNN accelerator dataflows.
• MAESTRO — An analytical cost model for DNN dataflows.

• Volta Architecture Whitepaper — The introduction of Tensor Cores.
• Dissecting the NVIDIA Volta GPU via Microbenchmarking — A detailed reverse-engineering of Tensor Core behavior.
• Dissecting Tensor Cores via Microbenchmarks — Programmability, performance, and precision across generations.
• Modal GPU Glossary — A clear reference for SIMT execution and GPU terminology.

• A Modern Primer on Processing in Memory — Mutlu et al.'s comprehensive introduction to PIM.
• PRIME: A Novel PIM Architecture for Neural Network Computation — ReRAM-based neural network acceleration in memory.
• Samsung HBM-PIM (Aquabolt-XL) — A commercialized processing-in-memory design.

The chips themselves, organized by class.

• NVIDIA Hopper Architecture Whitepaper — H100: FP8, the Transformer Engine, and TMA.
• NVIDIA Blackwell Architecture — The GB200/B200 generation for trillion-parameter models.
• AMD CDNA Architecture — The compute architecture behind the MI300 series.
• Dissecting the Ampere GPU Architecture — Microbenchmark-driven analysis of modern GPU internals.

• In-Datacenter Performance Analysis of a TPU (TPUv1) — Jouppi et al.'s landmark ISCA '17 paper.
• A Domain-Specific Supercomputer for Training DNNs (TPUv3/v4) — Google's system-level TPU design.
• TPU v4: An Optically Reconfigurable Supercomputer — Optical circuit switching for large-scale training.
• Ten Lessons From Three Generations of TPUs — Jouppi and Patterson on hardware-software co-design.

• Apple Machine Learning Research — Publications on the Apple Neural Engine and on-device ML.
• Coral / Edge TPU — Google's edge inference accelerator.
• MLPerf Tiny / TinyML — Benchmarks and models for microcontroller-class inference.
• Efficient Deep Learning (MIT 6.5940 / TinyML) — Song Han's course on model compression and edge deployment.
• A Survey of Accelerator Architectures for DNNs — Broad coverage of the accelerator design space.

• FINN — AMD/Xilinx's framework for quantized neural network inference on FPGAs.
• hls4ml — Translating ML models to FPGA firmware via high-level synthesis.
• Vitis AI — AMD/Xilinx's development stack for FPGA/ACAP inference.
• Brainwave: A Configurable Cloud-Scale DNN Processor — Microsoft's real-time FPGA AI serving.

• RISC-V Vector Extension (RVV) — The vector ISA extension for data-parallel workloads.
• RISC-V Specifications — The open ISA underpinning much accelerator research.
• Ara — A RISC-V vector processor from ETH Zürich's PULP platform.

Tools for exploring the design space before committing to silicon.

• gem5 — The de facto community architecture simulator.
• Accel-Sim — A framework for simulating and validating GPU architectures.
• GPGPU-Sim — Cycle-level simulation of NVIDIA GPUs running CUDA/OpenCL.
• SCALE-Sim — ARM's systolic-array CNN accelerator simulator.
• Timeloop / Accelergy — Mapping and energy/area modeling for DNN accelerators.
• Sparseloop — Analytical modeling for sparse tensor accelerators.
• ASTRA-sim — Distributed ML training platform and network co-design simulator.
• LLMCompass — Hardware evaluation for LLM inference.
• Roofline: An Insightful Visual Performance Model — Williams, Waterman, and Patterson's foundational model.

Following the people and publications that explain how chips are actually designed, built, and brought to market — the industry context that connects everything above.

• SemiAnalysis — Dylan Patel's deep dives on the semiconductor industry, AI hardware, and the supply chain.
• The EDA Primer: From RTL to Silicon — SemiAnalysis's end-to-end walkthrough of the chip design flow; the single best starting point for the big picture.

• Asianometry — Accessible, well-researched videos on semiconductor history, manufacturing, and the industry.
• CalebWritesCode — Hands-on GPU programming and low-level systems tutorials.
• Dwarkesh Patel — Long-form interviews with leading figures in AI and hardware.
• 3Blue1Brown — Grant Sanderson's visual explanations of the math and neural networks behind the workloads.

• brrrviz — An interactive visualization of GPU architecture and how modern GPUs go brrr.

Register-transfer-level design in Verilog and SystemVerilog — the entry point to any accelerator implementation. Start with the textbook, follow the lectures, then build fluency on the practice sites.

• Textbook — Digital Design and Computer Architecture, Harris & Harris. The standard undergraduate text taking you from logic gates to a working RISC-V processor.
• Lectures — Onur Mutlu — Digital Design & Computer Architecture (ETH Zürich). A complete, freely recorded lecture series widely regarded as the best online course on the subject.
• Practice — HDLBits. Interactive Verilog problems with instant feedback; the single most effective way to build RTL coding fluency.
• Reference — ASIC World. A free, comprehensive Verilog/SystemVerilog tutorial and syntax reference to keep open while you code.

Confirming the RTL does what it should — typically the majority of the effort on a real chip. Learn the methodology from the textbook, then practice UVM on the training sites.

• Textbook — SystemVerilog for Verification, Spear & Tumbush. The definitive introduction to the SystemVerilog features and testbench techniques used in industry.
• Lectures & Resources — Verification Academy. Siemens EDA's free hub of courses, the canonical UVM Cookbook, and methodology guides — the go-to reference for DV.
• Training — ChipVerify. Free, approachable SystemVerilog and UVM tutorials with worked examples, ideal for getting members productive quickly.
• Hands-on — cocotb. Write testbenches in Python instead of SystemVerilog; the most accessible on-ramp to writing real verification.

Turning a synthesized netlist into a manufacturable, timing-clean layout (synthesis → floorplan → placement → CTS → routing → timing/signoff). Ground yourself in the textbooks, then run a full flow hands-on.

• Textbook — VLSI Physical Design: From Graph Partitioning to Timing Closure, Kahng, Lienig, Markov & Hu. The standard text covering every stage of the physical design flow.
• Textbook (Circuits) — CMOS VLSI Design: A Circuits and Systems Perspective, Weste & Harris. The classic bridge from transistors and layout to full VLSI systems.
• Textbook (Timing) — Static Timing Analysis for Nanometer Designs, Bhasker & Chadha. The definitive reference for understanding timing closure.
• Lectures — NPTEL — VLSI Physical Design Automation. A complete, freely available lecture course on the algorithms behind each PD stage.
• Training — VLSI System Design (VSD). Popular hands-on courses and workshops that walk you through a real RTL-to-GDSII flow.
• Hands-on — OpenLane. An open, automated RTL-to-GDSII flow on the Sky130 PDK — the best way to actually run physical design end-to-end for free.

The best openly available courses across the stack.

• Stanford CS217 — Hardware Accelerators for ML — Systems and hardware for machine learning.
• Stanford CS149 — Parallel Computing — Kayvon Fatahalian's parallel programming course.
• MIT 6.5940 — TinyML & Efficient Deep Learning — Song Han's course on compression, quantization, and acceleration.
• MIT 6.172 — Performance Engineering — Squeezing performance out of modern hardware.
• CMU 15-418 — Parallel Computer Architecture — The classic parallelism course.
• CMU 10-414/714 — Deep Learning Systems — Build a deep learning framework from scratch.
• Berkeley CS152/252 — Computer Architecture — Krste Asanović's architecture sequence.
• ETH Zürich — Digital Design & Computer Architecture — Onur Mutlu's freely recorded lectures.
• UW CSE 599W — Systems for ML — Tianqi Chen's ML systems course.