This repository gathers basic knowledge of how to build circuits using VHDL and Verilog description languages. The circuits implemented are:
-
Notifications
You must be signed in to change notification settings - Fork 0
SaBuMa/FPGA-Design
Folders and files
| Name | Name | Last commit message | Last commit date | |
|---|---|---|---|---|
Repository files navigation
About
This is a repository all related to the creating of Verilog and VHDL projects and its implementation in a DE10-Lite FPGA Development Board
Topics
Resources
Stars
Watchers
Forks
Releases
No releases published
Packages 0
No packages published