Memory Model SoA vs AoS

Memory Model: SoA vs AoS

In baseband processing (like LTE/5G), 90% of the performance bottlenecks are not in the ALU (arithmetic logic unit), but in Memory Bandwidth and Cache Misses.

The Problem with AoS (Array of Structures)

A naive implementation of a resource grid might look like this:

struct Complex { float re; float im; };
Complex rx_grid[14][1200];

This is fatal for AVX2 and CUDA. When vector registers try to load 8 consecutive real parts for a matrix operation, they are forced to execute expensive memory Shuffle/Unpack instructions to untangle the interleaved imaginary parts.
Our Solution: Strict SoA (Structure of Arrays)
MMSE_CPP strictly adheres to an SoA memory layout for all IQ data grids. As defined in include/mmse/types.h:
struct PlanarGridViewF32 {
    std::array<const float*, 2> re{}; // Antenna 0 and 1 Real parts
    std::array<const float*, 2> im{}; // Antenna 0 and 1 Imaginary parts
};

Benefits:
 * AVX2/AVX-512: A single _mm256_loadu_ps instruction seamlessly loads 8 consecutive REs.
 * CUDA: Guarantees Coalesced Memory Access. A warp of 32 threads fetching 32 consecutive REs triggers a perfect 128-byte memory transaction, maximizing the GDDR6 VRAM bandwidth.