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TinyCoDesign

TinyCoDesign is a small FPGA hardware/software co-design demo for the DaVinci Pro 100T board (xc7a100tfgg484-2). It intentionally avoids a large NPU/GPU scope. The first hardware target is a UART-controlled scratchpad plus a tiny signed int8 dot-product accelerator.

The point is the full system loop:

  1. Host software builds commands.
  2. UART moves command frames to the FPGA.
  3. RTL decodes frames into register and scratchpad transactions.
  4. Software schedules larger work as many tiny accelerator jobs.
  5. Results return through the same command channel.

Directory Layout

  • hw/rtl: UART, packet protocol, scratchpad, dot core, board top.
  • hw/sim: self-checking xsim testbenches.
  • hw/constraints: board constraint files such as tiny_100t.xdc.
  • sw/python: Python protocol/runtime plus simulator-backed tests.
  • sw/cpp: C++ protocol/runtime and CLI.
  • examples: Python board/simulator demos.
  • docs: protocol and architecture notes.

Start with docs/tutorial_zh.md for a detailed Chinese walkthrough of the hardware architecture, host runtime, protocol, and software/hardware execution flow.

Public Source Release

The public repository should contain source, tests, constraints, examples, and documentation. Generated Vivado projects, local Vivado helper scripts, build outputs, and compiled executables are intentionally excluded by .gitignore:

  • exclude project/
  • exclude hw/vivado/
  • exclude build/ and Vivado run/report artifacts
  • exclude generated binaries such as *.exe

TinyCoDesign is released under the MIT License. If you import third-party RTL or other source files later, keep their license notices compatible with the public source release.

Hardware Interface

  • Clock: 50 MHz sys_clk
  • Reset: active-low sys_rst_n plus internal power-on reset
  • UART: 115200 8N1
  • USB-UART pins: uart_rxd=E14, uart_txd=D17
  • Reset pin: sys_rst_n=U7
  • LEDs: led[0]=busy, led[1]=done

The scratchpad has two 1024-byte banks. Bank A and Bank B hold signed int8 vectors. The dot core reads both banks and accumulates into a signed int32 result.

Run RTL Simulation

The public source release keeps the Verilog sources and self-checking testbenches, but not local Vivado automation scripts. Add hw/rtl/*.v and the target testbench from hw/sim to Vivado/xsim, then run the testbench.

Covered testbenches:

  • UART loopback
  • packet RX/TX
  • dot core
  • full byte-level system command flow
  • board-top binary command flow through tcd_top

If you keep private helper scripts locally, put them under ignored paths such as hw/vivado/ or build/.

Build Hardware In Vivado

Create a Vivado project targeting xc7a100tfgg484-2, add hw/rtl/*.v, set tcd_top as the top module, and add hw/constraints/tiny_100t.xdc. Then run synthesis and implementation in the Vivado GUI or your own local batch scripts.

Python

Run tests:

cd TinyCoDesign
python -m unittest discover -s sw\python\tests

Run simulator examples:

python examples\print_demo.py --sim --text "Hello from TinyCoDesign"
python examples\dot_demo.py --sim
python examples\matmul_demo.py --sim

Run on board after programming the bitstream:

python examples\print_demo.py --port COM5 --text "Hello from TinyCoDesign"
python examples\dot_demo.py --port COM5

Expected print output:

Hello from TinyCoDesign

Install pyserial if using a real serial port.

sw/python/pyproject.toml is kept so the Python runtime can be installed as a normal editable package. For board access, install the optional serial dependency:

cd TinyCoDesign
python -m pip install -e .\sw\python[serial]

C++

Compile and run a simulator smoke test:

cd TinyCoDesign
New-Item -ItemType Directory -Force -Path build\cpp | Out-Null
g++ -std=c++17 -I sw\cpp sw\cpp\tiny_cli.cpp -o build\cpp\tiny_cli.exe
.\build\cpp\tiny_cli.exe --sim ping
.\build\cpp\tiny_cli.exe --sim print "Hello from TinyCoDesign"
.\build\cpp\tiny_cli.exe --sim dot 1,2,-3,4 5,-2,7,1

On board:

.\build\cpp\tiny_cli.exe --port COM5 ping
.\build\cpp\tiny_cli.exe --port COM5 print "Hello from TinyCoDesign"

sw/cpp/CMakeLists.txt is kept for users who prefer CMake over a direct g++ command. It builds the same tiny_cli executable and links the Windows serial port support library when needed:

cd TinyCoDesign
cmake -S sw\cpp -B build\cpp
cmake --build build\cpp --config Release

Vivado GUI

The checked-in public source does not include project/. Recreate the project from hw/rtl and hw/constraints/tiny_100t.xdc; keep any generated Vivado project directory local.

Scope

This version does not use DDR3, Ethernet, CUDA, or a full NPU compiler. Larger matrix multiply is intentionally handled by host-side tiling over the tiny dot operation. DDR3/MIG can be added later as a separate lab once this control and data movement loop is stable.

License

MIT License. See LICENSE.

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Minimal FPGA hardware/software co-design demo with UART protocol, scratchpad memory, and an int8 dot-product accelerator, plus Python/C++ runtimes.

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