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Load Store vs Read Write
This page clarifies the distinction between CPU load/store operations and memory controller read/write traffic, which is essential for understanding Mess measurements.
There's often confusion between:
- Loads/Stores: CPU instructions that access memory
- Reads/Writes: Actual traffic on the memory bus
These are not the same due to caches, prefetchers, and memory controller behavior.
The benchmark itself runs a traffic generator kernel that is configured to issue a specific load/store pattern. This is, loads / (loads + stores). Where 0% means this is a 100% store traffic generator and 100% means this is a 100% load traffic generator.
When we ISSUE the requests, we talk about loads and stores. The actual instructions in the assembly file are loads and stores. We cannot guarantee that ratio will be preserved when reading the ACTUAL read and write counters in the memory controller.
Whenever we talk about measured values, we will talk about reads and writes, and read ratio. Whenever we talk about issued values, we talk about loads and stores.
| Mess Parameter | Meaning |
|---|---|
--ratio=100 |
100% CPU load instructions, 0% stores |
--ratio=50 |
50% CPU loads, 50% CPU stores |
--ratio=0 |
0% CPU loads, 100% CPU stores |
This sets up the ISSUED ratio/s we want to run, and since that is issued, it would have to be loads and stores, NOT reads and writes.
Mess measures memory controller traffic, not CPU operations:
-
ReadBytes: Data read from DRAM -
WriteBytes: Data written to DRAM
For the Mess Profiler, we use ReadBytes and WriteBytes for the same reason. These are measured reads and writes.
- Temporal vs Non-Temporal stores - Store instruction variants
- Understand output - Output file interpretation
- Traffic Generator - How traffic is generated
