[Scala3] Rewrite svsim Verilator backend argument stringification

[adkian-sifive]

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In Scala 3, stringification of C++ arguments in the svsim Verilator backend was leading to the arguments being wrapped in brackets instead of a space-joined string. This change updates the argument generation to stringify arguments individually before joining them, fixing the problem in Scala 3 testing

Type of Improvement

• Internal or build-related (includes code refactoring/cleanup)

Desired Merge Strategy

• Squash: The PR will be squashed and merged (choose this if you have no preference).

Release Notes

Svsim Verilator Backend argument generation was refactored to work with Scala 3

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[seldridge]

LGTM

This entire file is very messy at this point. This isn't the fault of this PR, though. We can clean this up after Scala 3 gets turned on.

[jackkoenig]

I don't have a strong objection to this, but I would like a more detailed explanation for what exactly was different about Scala 3 here. Can you provide a simple example of the different? Are we sure this can't be fixed with a simpler change to toCommandlineArgument?

[adkian-sifive]

Issue is that in Scala 3 a Seq[Seq[String]] flattened and stringified as

@main def main =
  val cflags: Seq[Seq[String]] = Seq(
    Seq("-std=c++17"),
    Seq("-I$(shell pwd)"),
    Seq("-DSVSIM_ENABLE_VERILATOR_SUPPORT")
  )

  val buggy = cflags.flatten.mkString(" ")
  println(buggy)

prints [-std=c++17] [-I$(shell, pwd)] [-DSVSIM_ENABLE_VERILATOR_SUPPORT], while in Scala 2 it's space-separated as -std=c++17 -I$(shell pwd) -DSVSIM_ENABLE_VERILATOR_SUPPORT.