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Chisel v3.5.0

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@jackkoenig jackkoenig released this 12 Jan 07:06
v3.5.0
29df513

Please see the porting guide for upgrading from Chisel 3.4.[1]

Chisel is built on top of FIRRTL so some FIRRTL changes can affect Chisel users, please see the FIRRTL v1.5.0 release notes as well.

Highlights

  • Definition/Instance introduces a new experimental API for module instantiation that disentagles elaborating the definition (or implementation) from instantiation of a given module. This solves Chisel's longstanding reliance on "Deduplication" for generating Verilog with multiple instances of the same module. Please see the dedicated cookbook for more information. (#2045)
  • DataView is an experimental mechanism for "viewing" Scala objects as a subtype of Data. Often, this is useful for viewing one subtype of Data, as another. One can think about a DataView as a cross between a customizable cast and an untagged union. It enables some very powerful design patterns. Please see the documentation and cookbook for more information. (#1955)
  • viewAsSuperType is a new mechanism for treating Bundles as if they were an instance of a parent type. It solves a longstanding issue with bulk connecting Bundles when there is an inheritance relationship between them [#661]. See the DataView cookbook for more details.
  • Vec Literals provide a mechanism similar to BundleLiterals for creating literal Vecs. Please see the associated documentation for more details. (#1834)
  • Seq/Tuple implicit conversions built on top of DataView make certain design patterns much more intuitive. These conversions are available by import chisel3.experimental.conversions._. See the related section of the DataView explanation for more details. (#2277)

Feature

  • ExtModule now supports built in support for providing Verilog source (#1154)
  • Naming improvements
    • When prefixing with a data, eagerly get local name (#1614)
    • Use Data refs for name prefixing with aggregate elements (#1616)
    • Added Force Name API (#1634)
  • add new APIs to BitPat (#1819)
    • add Y, N, select, slice, and ## to BitPat.
    • Add toString method to BitPat
  • Verification
    • Guard statements with module reset (#1891)
    • create and extend annotatable BaseSim class for verification nodes (#1968)
    • Make printf return BaseSim subclass so it can be named/annotated (#1992)
  • Implement Espresso Decoder (#1914)(#1964)
  • Add when.cond for getting the current when condition (#1694)
  • add ShiftRegisters to expose register inside ShiftRegister.
  • Parametrized Mem- & SyncReadMem-based implementation of the Queue class (#1740)
  • Import memory files inline for Verilog generation (#1805)
  • Make plugin autoclonetype always on (#1826)
  • Add getVerilog in Chisel3 (#1921)
  • Merge minimized table before return as a TruthTable (#1933)
  • Add isOneOf method to ChiselEnum (#1966)
  • Add BitSet API (#2211)
  • Improve Data.toString (#2197)
  • implement trace API. (#2077)
  • Circular-shift (rotate) operations for UInt (#1140)
  • Added flush capability to Queue (#2030)
  • Added VecInit factory methods (fill,iterate)(#2059)
  • Add multiple dimensions to VecInit fill and iterate (#2065)

API Changes

  • Bundles can no longer be instantiated with bound hardware
  • Bundles no longer can be instantiated with bound types
  • Stop Emitting BlackBoxResourceAnno. This removes the - need for a FIRRTL compiler to grok the Java Resource API in order to handle BlackBoxResourceAnno. (#1954)
  • Require the chisel3 compiler plugin (#2271)
    The chisel3 compiler plugin is now required. See https://github.com/chipsalliance/chisel3#build-your-own-chisel-projects for instructions on how to add it to your project.
  • Refactor TruthTable to use Seq (#2217) -- this is changed from RC1
  • Remove v3.4.0 version of autoNameRecursively (#2149)
  • Remove .toBools (#2170)
  • Remove ChiselExecutionOptions and HasChiselExecutionOptions (#2267)
  • refactor Queue.hasFlush: Boolean to Queue.flush: Option[Bool]. (#2245) -- change from RC1
  • Remove all Bundle cloneTypes and chiselRuntimeDeprecate its use (#2052)
    This is technically an API change but due to the new chisel3 compiler plugin requirement, it should not affect users

API Deprecations

  • deprecate getPorts with modulePorts. (#1945)
  • deprecate getModulePorts (#2284)
  • Deprecate chisel3.internal.firrtl.Port (#2302)
    Deprecate (instead of removing) chisel3.internal.firrtl.Port. Fix deprecation warnings on public APIs that return this type and add ScalaDoc to replacement APIs.
  • Deprecate chisel3.BackendCompilationUtilities (#2257)
  • Deprecate computeName (#2192)
  • Add nullary .fire to Valid and deprecate dummy version (#2156)
  • Deprecate auto-application of empty argument lists to parameterless functions (#2124)
  • Remove Deprecated APIs (#1730)
  • remove 2.11 dedicated code. (#1744)
  • 8a73362 Remove val io
  • 7e4d1ee Update docs for the removal of val io and MultiIOModule
  • 6c6ec71 Fold Chisel.CompatibilityModule into chisel3.internal.LegacyModule

BugFix

  • catch None.get in BitPat.apply(x: UInt): BitPat (#2276)
  • Fix isACloneOf (#2205)
  • Definition name index skipping with D/I (#2249)
  • Fixed bug with unary minus on FixedPoint and Interval (#2154)
  • Fix naming of unwrapped val io in Chisel.Modules (#2150)
  • Fix chisel3 <> for Bundles that contain compatibility Bundles (#2031)(#2097)
  • Fixing aspect injection context bug (#1874)
  • Make it legal for concrete resets to drive abstract reset (#2018)
  • Fix chisel3 <> for Bundles that contain compatibility Bundles.
  • BiConnect in chisel3 delegates to FIRRTL <- semantics whenever it hits a
  • Bundle defined in import Chisel._. (#2023)
  • Fix higher-kinded types for autoclonetype (#2121)
  • Fix bug where refs may not get set for Records (#1645)
  • SeqUtils asUInt endian-ness: hi/lo instead of right/left (#1647)
  • Bugfix - adding external modules was broken (#1649)
  • Improve source locators for switch statements. (#1669)
  • Fix RegInit of Bundle lits (#1688)
  • Fix incorrect usage of emitFirrtl in test (#1817)
  • Don't toggle top.cpp clock and reset on same cycle (#1820)
  • Fix ShiftRegister with 0 delay. (#1903)
  • implement model checking API for chiseltest (#1912)
  • Fix CloneModuleAsRecord support for .toTarget (#1974)
  • Fix aop.Select behavior for CloneModuleAsRecord (#1993)
  • Fix ChiselEnum warnings and use Logger for warnings instead of println (#1999)
  • Fix a bug causes incorrect pla generation when input is ?(#2113)

Dependency Bumping

  • Update sbt to 1.5.7 (#2303)
  • Update sbt to 1.5.6 (#2300)
  • Update os-lib to 0.8.0 (#2301)
  • Add scala 2.13.7 to plugin build list (#2228)
  • Update sbt-mima-plugin to 1.0.1 (#2176)
  • Update sbt-ci-release to 1.5.10 (#2183)
  • Update sbt-scalafix to 0.9.33 (#2262)
  • Update sbt-site to 1.4.1 (#1676)
  • Update sbt-unidoc to 0.5.0
  • Update sbt-mdoc to 2.2.24 (#2196)
  • Update sbt-scoverage to 1.9.2 (#2229)
  • Update sbt-ci-release to 1.5.9 (#2139)
  • Update scalatest to 3.2.10 (#2140)

Miscellany

  • Lazy .fir Emission, use BufferedCustomFileEmission in CircuitSerializationAnnotation (#2083)
  • Also add newline to end of verilog modifier code blocks so that there is always a newline between code blocks and following material. (#2016)
  • Provide user source locators in Builder.error errors (#1618)
  • Enable Cat of Zero Element Vec (#1623)
  • Make -e option work with ChiselStage methods (#1630)
  • Remove Data.setRef assertion (#1654)
  • For HasId.setRef, have first set win (with force override) (#1655)
  • Refine autonaming to have more intuitive behavior (#1660)
  • Add custom mdoc modifier for emitted Verilog (#1666)
  • (encore) Builder: use LazyLogging.logger.warn to print elaboration message (#1670)
  • 3bea616 [plugin] Disable BundleComponent by default, add option to enable
  • a8d3238 [plugin] Stop autoclonetype stack traces when using plugin
  • 1494231 [plugin] Implement autoclonetype in the compiler plugin
  • e80e9a3 [plugin] Split ChiselComponent into its own file
  • 0a0d7c6 Make it possible to GC Data instances
  • 53b6204 Add no-plugin-tests for testing Chisel without the compiler plugin
  • add helper function to convert chirrtl to firrtl. (#1854)
  • b88ae1f Deprecate override_clock and override_reset in Module
  • 5ece5aa Rename MultiIOModule to Module
  • b96e7dd farewell Scala 2.11
    • use Seq.iter for oneline implementation. (#1723)
  • Expose AnnotationSeq to Module. (#1731)
  • Fix Mergify condition for labeling backports (#1742)
  • Refactor EnumAnnotations and EnumFactory (#1747)
  • Update reported width from div/rem to match FIRRTL results (#1748)
  • Scala 2.13 support (#1751)
  • Fix some typo and using foreach instead of map in BoringUtils (#1755)
  • Fix incorrect comment in ScalaDoc (#1756)
  • Bump to Scala 2.12.13 (#1766)
  • Fix stack trace trimming across Driver/ChiselStage (#1771)
  • Remove chisel3.stage.phases.DriverCompatibility (#1772)
  • Add file line to source link from scaladoc (#1776)
  • Fix conversions between DecoupledIO and IrrevocableIO (#1781)
  • Aggregate: fix typo (#1789)
  • [docs] MovingAverage3 => MovingSum3, The example in the README is a sum, not an average. (#2050)
  • [docs] Fix broken mdoc (#1600)
  • [docs] Move more docs (#1601)
  • [docs] Move Chisel3 to SPDX license conventions (#1604)
  • [docs] Small changes to memory doc (#2062)
  • [docs] Fixed broken link to type hierarchy diagram (#1611)
  • [docs] Delete index.md (#1613)
  • [docs] Fix crosslinks in mdoc. Can't use md suffix (#1640)
  • [docs] Fix broken links in docs (#1643)
  • [docs] Ignore tests using System.setSecurityManager (#1661)
  • [docs] Update some README links to chipsalliance (#1673)
  • [docs] readme: simplify sbt snippet and update to the latest stable release (#1686)
  • [docs] Adding ChiselEnum Documentation Entry (#1795)
  • [docs] Minor docs improvements (#1774)
  • [docs] Reorganize website docs (#1806)
  • [docs] Update the FAQ and add doc on versioning (#1827)
  • [docs] Provide useful message on Vec.apply require (#1838)
  • [docs] Fix formatting issue of links (#1844)
  • [docs] Fix Gitter chat room link (#1848)
  • [docs] Add documentation guide about memory initialization (#1850)
  • [docs] Add "how to tie off to 0" to the Cookbook (#1857)
  • [docs] Add a link to the Chisel book (#1872)
  • [docs] Update type_hierarchy (#1979)
  • [docs] Add example of stripping directions from type (#2074)
  • Improve exception message for aliased bundle fields (#2304)
  • [docs] Add "Upgrading From Chisel 3.4 to 3.5" (#2275)
  • Better MonoConnect error messages (#2248)
  • Add support for dynamic indexing on Vec identity views (#2298)
  • [docs] Update versioning appendix to include 3.5 (#2293)
  • [docs] Remove body from minimizing output bits recipe (#2290)
  • [docs] add minimizing output bits recipe (#2278)
  • reduceTree() now operates on Seq (#2292)
  • Add Hierarchy trait (#2204)
  • add documentation to decoder. (#2254)
  • Update bundles-and-vecs.md (#2173)
  • Update experimental-features.md (#2175)
  • Add field grouping ScalaDoc for ArbiterIO (#2208)
  • Add field grouping ScalaDoc for other subclasses of Bundle (#2214)
  • Exposing more APIs from D/I internals (#2220)
  • Add Select APIs for Hierarchy package (#2210)
  • Add java reflection to hierarchy (#2209)
  • [docs] Improve tieoff Bundle to 0 (#2218)
  • Fix GaloisLFSR comments (#2178)
  • [docs] Remove workaround for fixed issue in mdoc crash blocks (#2147)
  • Fix typos in documentation (#2141)
  • verification: fix off by one error in deprecation message (#2135)
  • make all verification statements publically available (#2089)

[1] You can contribute to the porting doc by opening PRs against https://github.com/chipsalliance/chisel3/blob/master/docs/src/appendix/upgrading-from-chisel-3-4.md

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