2. Circuit Design

Circuit Design

System Block Diagram

System-Level Architecture

This system is designed as a fully integrated active speaker application

• High-performance ADC Analog front-end (balanced/unbalanced)
• Multi-source digital input (S/PDIF, USB, Raspberry Pi)
• DSP core (SigmaDSP)
• Digital power amplifier (Class-D, I2S/TDM input)
• Control subsystem (PIC MCU)

RCA-pin Input :

• OPA1612 buffer (voltage follower)
• Low noise (~1.1 nV/√Hz)
• Excellent linearity
• High input impedance(=47kΩ) fits the Consumer equipment
• Ground Lift Strategy reduces hum noise (50/60 Hz)

Balanced XLR-Input :

• Fully Balanced Driver (OPA1632)
• Allow small potential differences between equipments
• Low Impedance Design reduces Johnson (thermal) noise:
• Symmetrical output swing
• Low THD+N (< -100 dB class)

Double Differential ADC Circuit(AK5554) :

• Cancel even-order distortion
• Improve common-mode rejection ratio(CMRR) & Linearlities
• Increase dynamic range (SNR)

AUX-ADC Input Circuit :

ADAU1452/1466 includes 6 AUX ADCs.Two trimmer potentiometers are mounted on the board:

• RV1: Crossover frequency or low-frequency gain correction
• RV2: Tweeter delay time or high-frequency gain correction
• External potentiometers can also be connected if the RV1 and RV2 are removed.

Power Amplifier Circuit :

• TAS6424 4-channel Class-D amplifier
• 2.1 MHz PWM switching

• Digital Input: I2S (96kHz TDM)
• BTL mode enables high current output (not yet implemented)
• Speaker detection function prevents output if no speaker connected
• RGB LED D3 indicates:
  ◦Blue: power-on
  ◦Green: mute
  ◦Red: fault

Power Supply for Analog Circuit :

• Uses +10V and -5V rails for proper op-amp operation.
• Negative supply is generated using LM2611 and filtered with choke + electrolytic capacitors.

S/PDIF Input Circuit :

Original design supports optical and coaxial inputs without switching
(only one can be used at a time)

DSP Clock Driver Circuit & Selfboot Jumper JP4:

• 24.576 MHz clock (256fs @ 96kHz)
• Buffered and distributed to ADC and amplifier
• JP4 Disables EEPROM boot when shorted (for recovery from faulty firmware)

DSP Configuration Circuit :

• I2C used instead of SPI Slave port (slower but sufficient)
• DSP writes firmware to SPI EEPROM via its SPI master port
• Series resistor added to avoid EEPROM access failure issues
• USBi overrides I2C when connected

Power ON/OFF Muting

• Mute control linked to 24V supply voltage change
, which prevents pop noise during power transitions